Use 'enum cb_err' values for below cse lite functions instead of true or
false.
Functions whose return values updated in this patch:
1. cse_set_next_boot_partition()
2. cse_data_clear_request()
3. cse_set_and_boot_from_next_bp()
4. cse_boot_to_rw()
5. cse_fix_data_failure_err()
TEST= Do boot test on Gimble.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7fec530aeb617bab87304aae85ed248e51a6966b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It has been reported that the PEIM graphics driver may temporarily
fail communication with the display if the time between libgfxinit
turning off the displays and the PEIM driver initialization is too
short. 200 ms has been identified as a safe delay.
This is a temporary workaround and an investigation is in progress to
come up with a better and long term solution.
BUG=b:264526798
BRANCH=firmware-brya-14505.B
TEST=Developer screen is systematically seen
Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces an early graphics driver which can be used in
romstage in cache-as-ram mode. The implementation relies on
`libgfxinit' and provide VGA text mode support.
SoCs wanting to take advantage of this driver must implement the
`early_graphics_soc_panel_init' function to set the panel power
sequence timing parameters.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=Graphics bring up observed on skolas with extra patches
Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A mainboard port needs to:
- select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT'
- implement the Ada package `GMA.Mainboard' with a single function
`ports' that returns a list of ports to be probed for displays.
- set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use
in romstage (and ramstage) for the graphic device.
BUG=b:252792591
BRANCH=firmware-brya-14505.B
TEST=libgfxinit compiles in romstage.
libgfxinit successfully executes in romstage and ramstage using
the requested MMIO setting on skolas.
Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch adds Kconfigs to define scaling factor for Efficient and
Performance cores instead of using hard coded values in the soc code.
Also, the patches uses the Kconfigs directly to calculate the core's
nominal performance. So, we don't need to implement soc function
soc_get_scaling_factor() to get the scaling factor data for different
core types. Hence, soc_get_scaling_factor() function is removed.
TEST=Build the code for Gimble and Rex. Also, I have verified that
build system logs error when the Kconfigs are undefined.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
get_cpu_index() helper function returns cpu's index based on it's APIC
id position from the ascending order list of cpus' APIC IDs.
In order to calculate the cpu's index, the helper function needs to
traverse through each cpu node to find their APIC IDs. So, the function
traverse the CPU node list from the cpu whose APIC ID is 0 assuming it
is the first cpu node in the list. This logic works fine where BSP's
APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as
APIC ID numbering first get assigned for CPU Die Efficient cores, then
Performance cores.
Please refer section# 6.1 of doc#643504 for more details on APIC IDs.
Considering the APIC Id allotment for MTL cores, as existing code
traversing begins from the cpu that has APIC Id#0 which may not be the
first cpu node in the list so index calculation results in wrong value.
The patch addresses above described issue by traversing all the CPU
nodes to calculate the cpu index. Also, prevents inconsistent report
of /sys/devices/system/cpu/cpu*/cpufreq/* and
/sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot.
TEST=Verified that the get_cpu_index helper function returns the correct
index id for a CPU on Rex.
The coreboot log with code instrumentation, before this patch:
[DEBUG] my_apic_id:0x10 cpu_index: 0x6
[DEBUG] my_apic_id:0x11 cpu_index: 0x6
[DEBUG] my_apic_id:0x42 cpu_index: 0x6
[DEBUG] my_apic_id:0x21 cpu_index: 0x6
[DEBUG] my_apic_id:0x40 cpu_index: 0x6
[DEBUG] my_apic_id:0x31 cpu_index: 0x6
[DEBUG] my_apic_id:0x39 cpu_index: 0x6
[DEBUG] my_apic_id:0xa cpu_index: 0x3
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x8 cpu_index: 0x2
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x28 cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x38 cpu_index: 0x6
[DEBUG] my_apic_id:0x29 cpu_index: 0x6
[DEBUG] my_apic_id:0xe cpu_index: 0x5
[DEBUG] my_apic_id:0x6 cpu_index: 0x2
[DEBUG] my_apic_id:0x20 cpu_index: 0x6
[DEBUG] my_apic_id:0x30 cpu_index: 0x6
[DEBUG] my_apic_id:0x19 cpu_index: 0x6
[DEBUG] my_apic_id:0xc cpu_index: 0x4
[DEBUG] my_apic_id:0x18 cpu_index: 0x6
We can see same cpu_index for multiple cores before fix.
After this patch..
[DEBUG] my_apic_id:0x10 cpu_index: 0x8
[DEBUG] my_apic_id:019 cpu_index: 0xb
[DEBUG] my_apic_id:0x11 cpu_index: 0x9
[DEBUG] my_apic_id:0x18 cpu_index: 0xa
[DEBUG] my_apic_id:0x40 cpu_index: 0x14
[DEBUG] my_apic_id:0x30 cpu_index: 0x10
[DEBUG] my_apic_id:0x42 cpu_index: 0x15
[DEBUG] my_apic_id:0xc cpu_index: 0x6
[DEBUG] my_apic_id:0x2 cpu_index: 0x1
[DEBUG] my_apic_id:0x29 cpu_index: 0xf
[DEBUG] my_apic_id:0xe cpu_index: 0x7
[DEBUG] my_apic_id:0x20 cpu_index: 0xc
[DEBUG] my_apic_id:0x0 cpu_index: 0x0
[DEBUG] my_apic_id:0x31 cpu_index: 0x11
[DEBUG] my_apic_id:0x28 cpu_index: 0xe
[DEBUG] my_apic_id:0x21 cpu_index: 0xd
[DEBUG] my_apic_id:0xa cpu_index: 0x5
[DEBUG] my_apic_id:0x38 cpu_index: 0x12
[DEBUG] my_apic_id:0x8 cpu_index: 0x4
[DEBUG] my_apic_id:0x4 cpu_index: 0x2
[DEBUG] my_apic_id:0x39 cpu_index: 0x13
Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PRMRR is used by many Intel SOC features, not just Intel SGX.
As of now SGX and Key Locker are the features that need PRMRR.
Untie it from Intel SGX specific files and move to common cpulib.
Also rename PRMRR size config option. Use the renamed PRMRR size
config option to set the PRMRR size.
TEST=Able to set PRMRR size using config.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
The patch addresses Intel heterogeneous cores as `Efficient` and
`Performance` cores instead of `small` and `big` cores. It is to ensure
coreboot code has uniform reference to the heterogeneous cores. So, the
patch renames all `small` and `big` core references to `efficient` (eff)
and `performance` (perf) cores respectively.
TEST=Build the code for Brya and Rex boards
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add below mentioned functions:
is_sgx_configured_and_supported():
Checks if SGX is configured and supported
is_keylocker_configured_and_supported():
Checks if Key Locker is configured and supported
check_prm_features_enabled():
Checks if any of the features that need PRM are configured
and supported. As of now SGX and Key Locker are the only
features that need PRM.
Also, call check_prm_features_enabled() from get_valid_prmrr_size()
to make sure PRM dependent features are enabled and configured before
returning PRMRR size.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
BUG=none
TEST=Verify presence of subsystem ID for fast_spi device on google/rex.
lspci output before this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
lspci output after this patch:
00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23]
Subsystem: Intel Corporation Device [8086:7e23]
Note: UPD SiSkipSsidProgramming was set to 1 for above test.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch moves API "smbios_cpu_get_max_speed_mhz()"
to common code from board specific. This API was made
generic in 'commit d34364bdea ("soc/intel/alderlake:
Utilize `CPU_BCLK_MHZ` over dedicated macro")'
BUG=NONE
TEST=Boot and verified that SMBIOS max speed value is
correct on brya and rex.
(brya) dmidecode -t : "Max Speed: 4400 MHz"
(rex) dmidecode -t : "Max Speed: 3400 MHz"
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I87040ab23319097287e191d7fc9579f16d716e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel doc#630774, BIOS should clear Host Interrupt Status
if it has read all the slots of the message from the ME circular buffer.
Since this is not found in client ME document, add a Kconfig
SOC_INTEL_CSE_SERVER_SKU that only clears interrupt status for Server
ME SKU.
On SPR-SP, if mainboard calls get_me_fw_version via HECI-1, with the
change can avoid seeing below Linux warning during boot with Linux
v5.12:
[ 17.868929] irq 16: nobody cared (try booting with the "irqpoll" option)
[ 17.883819] CPU: 10 PID: 0 Comm: swapper/10 Not tainted 5.12.0
[ 17.902412] Hardware name: Wiwynn Crater Lake EVT2/Crater Lake-Class1
[ 17.922327] Call Trace:
[ 17.927780] <IRQ>
[ 17.932253] dump_stack+0x64/0x7c
[ 17.939640] __report_bad_irq+0x37/0xb1
[ 17.948206] note_interrupt.cold.11+0xa/0x63
[ 17.957713] handle_irq_event_percpu+0x6a/0x80
[ 17.967626] handle_irq_event+0x2a/0x50
[ 17.976163] handle_fasteoi_irq+0x9e/0x140
[ 17.985305] __common_interrupt+0x38/0x90
[ 17.994255] common_interrupt+0x7a/0xa0
[ 18.002821] </IRQ>
[ 18.007514] asm_common_interrupt+0x1e/0x40
Change-Id: I1cf21112870e53a11134d43e461b735ead239717
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Clang generates R_X86_64_32S symbols that get truncated.
TESTED:
- prodrive/hermes boots with GCC and clang
- MTRR are properly cleared (tested by filling in both
MTRR_FIX_64K_00000 and MTRR_FIX_4K_F8000 before clearing)
Change-Id: I6a5139f7029b6f35b44377f105dded06f6d9cbf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch skips sending CONN IPC command to PMC if system is resuming
from S3.
Sending CONN IPC command as part of `tcss_configure_dp_mode()` function
results into ERROR while system is resuming from S3.
Additionally, skip `configure_aux_bias_pads()` during S3 resume.
BUG=b:260984500
TEST=Able to test on Google/Rex.
Without this patch:
[ERROR] pmc_send_ipc_cmd status: fatal
[ERROR] Port 1 connect request failed
[SPEW ] [TCSS] TcssInit() - End
With this patch:
No error seen during S3 resume.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1dab7dc8b4ad76ca0c9630456803c1b9a320fe40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
BUG=b:259716145
TEST=Dump SSDT and see that _PRW and _DSD for CNVi device contains
the value from the devicetree on google/redrix.
Before:
Scope (\_SB.PCI0.WFA3)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
After:
Scope (\_SB.PCI0.CNVW)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x6D,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
})
...
}
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ia4ffedcb53afe350694eb03a144d12f714190cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70447
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves TCSS firmware latency related macros from SoC
specific tcss.h to IA common tcss.h
Additionally, ensure other structure definitions belonging to the
IA common code tcss.h are not causing compilation issues for ASL files
(due to including FW latency macros) hence, guarded against
`!defined(__ACPI__)`.
TEST=Able to build and boot Google/Rex and Google/Kano.
Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are four requirements for the SMI to hit a printk()
this commit now removes.
Build must have DEBUG_SMI=y, otherwise any printk() is a no-op
inside SMM.
ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value.
Platform needs to have IO Trap #3 enabled at IO 0x800.
The SMI monitor must call io_trap_handler for IO Trap #3.
At the moment, only getac/p470 would meet the above criteria
with TRAP(0x32) in its DSDT _INI method. The ASL ignores any
return value of TRAP() calls made.
A mainboard IO trap handler should have precedence over
a southbridge IO trap handler. At the moment we seem to have
no cases of the latter to support, so remove the latter.
Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This replaces the mechanism with --ext-win-base --ext-win-size with a
more generic mechanism where cbfstool can be provided with an arbitrary
memory map.
This will be useful for AMD platforms with flash sizes larger than 16M
where only the lower 16M half gets memory mapped below 4G. Also on Intel
system the IFD allows for a memory map where the "top of flash" !=
"below 4G". This is for instance the case by default on Intel APL.
TEST: google/brya build for chromeos which used --ext-win-base remains
the same after this change with BUILD_TIMELESS=1.
Change-Id: I38ab4c369704497f711e14ecda3ff3a8cdc0d089
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.
1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.
During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).
Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.
The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.
Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.
The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
