Add new memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B
2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E
3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP
4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H9JCNNNBK3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 1 (0001)
H9JCNNNCP3MLYR-N6E 2 (0010)
BUG=b:292461498
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Set the cs_pi_start_high_in_ect if the DUT is using one of the two
following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to
set cs_pi_start_high_in_ect when using these parts will result in an
MRC cache failure and DUT will fail to boot.
BUG=b:292153199
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya
variant to kernel.
Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With currently set default PSP_SOFTFUSE_BITS for phoenix SoC,
the non-serial build does not boot on Myst.
Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get
the non-serial build booting.
The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA).
BUG=b:292489356
TEST=Flash image-myst.bin, verify that it's able to boot on Myst
proto0.
Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: Ica3756e117fc58166958f37e7b007abb79d9d350
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76744
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: Ie1d882cac90211541a636d2dab297c343a12d66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76743
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Necessary to allow coolstar's Windows touchpad driver for this board,
since the touchpad is attached to the SMBus. The VID/DID combo used is
not registered/doesn't conflict with any currently in use, and would
be difficult to change at this point since the Windows drivers have
already been signed.
TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify
touchpad driver works properly.
Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
After switching to S3, it was found that drives on the SATA port do not
exit D3cold on S3 exit. Disable RTD3 on the port until the issue can be
resolved.
Avoids the following error in Linux:
pcieport 0000:00:1d.0: Unable to change power state from D3cold to D0, device inaccessible
Tested on darp8 with a Samsung 970 EVO or Crucial P5 in J_SSD1.
Change-Id: Ib26f59db61acfbf9248cea379c197765d3d9c470
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76593
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit e33d253793 ("soc/amd/common/block/acpi/ivrs: fix
missing IOAPIC[1] error").
Now that the per PCI root domain IOAPIC MMIO resource is reported on the
domain device, we can again probe the resource on the domain device
instead of the northbridge PCI device in that domain. This will make the
IVRS code compatible again with the work in progress Genoa SoC support.
TEST=Linux doesn't complain about the IOAPIC[1] missing in the IVRS on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib861b19d798fc8ee6603e8803d8d1939be08d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76659
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Call read_non_pci_resources from amd_pci_domain_read_resources to tell
the resource allocator about the non-PCI MMIO regions within the data
fabric MMIO regions so that the allocator won't place any PCI MMIO in
the same areas.
TEST=On Mandolin 3 new non-PCI resources get reported to the allocator:
avoid_fixed_resources: DOMAIN: 0000 04 base fd100000 limit fd1fffff mem (fixed)
avoid_fixed_resources: DOMAIN: 0000 05 base fd000000 limit fd0fffff mem (fixed)
avoid_fixed_resources: DOMAIN: 0000 20000120 base fec01000 limit fec01fff mem (fixed)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7f69b86e376e3368d4f156ccf93791cc00886489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Introduce the common read_non_pci_resources function to read the base
address of the non-PCI resources within the MMIO regions configured in
the data fabric registers and pass that info to the resource allocator.
Each SoC will need to provide implementations for get_iohc_misc_smn_base
and get_iohc_non_pci_mmio_regs in order for read_non_pci_resources to
know the SoC-specific base addresses, register offsets and MMIO region
sizes. In case of SoCs with only one PCI root domain, the domain
parameter of get_iohc_misc_smn_base will be unused, but in the case of
SoCs with more than one PCI root domains, this parameter will be used by
the SoC-specific code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If9aca67fa0f5a0d504371367aaae5908bcb17dd9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The SuperIO is not used so don't enable decoding of 0xE2 and
drop all code using it. It's not even required for the virtual
UART on 0x3f8 to work.
Add the virtual UART on 0x3f8 as ACPI device.
TEST: Verified on SBP1 that serial still works.
Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add pujjo new supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Hynix H58G56BK7BX068
2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:292452868
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From ccache(1):
mtime
Hash the compiler’s mtime and size, which is fast. This is the default.
Hashing the compiler binary's content would only be necessary when we
expect different binaries of the same size with the same path (e.g.
during a compiler bootstrap) and wrong modification timestamps (might
happen when checking an older version out of a (package) repository).
Neither should be the case during our builds. And even if everything
fails at once, chances are additionally low that a wrong cache hit
would cause a problem.
tl;dr we're building and testing firmware, not toolchains.
Change-Id: I264a72c628559384fcc2060d777c52af927d5e14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
There were some issues with the current Linuxboot Makefiles.
- multithreaded compilation didn't work, because some prerequisites
were missing
- initramfs wasn't added for x86 qemu boot.
- riscv support was incomplete
It began with separate patches, but resulted in a clean up patch, that
is hard to separate. The most important changes are the following:
- Instead of phony targets, actual files are now used as prerequisites
- riscv can now be used as target
- initramfs works now also for x86
- instead of querying the most recent version from the internet, I set a
known working version (because I tested it) that can be customized
and/or upgraded in the future. The reasons:
- querying the version from the internet requires a constant
connection to the internet even after linux kernel is already
build (aka subsequent builds).
- one usually wants to use a known working version, but optionally
still have the posibillity to choose a custom one. This patch
introduces this possibility in its most simple form.
- I removed as much ifeq statements as possible and moved that
responsibility to Kconfig, because they tend to make the
Makefile less readable.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25e757108e0dd473969fe5a192ad0733f1fe6286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76150
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.
BUG=b:268546941
TEST=Verified the settings on google/brya using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
