Commit Graph

2241 Commits

Author SHA1 Message Date
Edward O'Callaghan
1104c278e3 cpu/x86/smm: Fix explicit 'addr32' usage in clang builds
The addr32 prefix is required by binutils, because even when
given an explicit address which is greater than 64KiB, it will
throw a warning about truncation, and stupidly emit the opcode
with a 16-bit addressing mode and the wrong address.

However, in the case of LLVM, this doesn't happen, and is happy
to just use 32-bit addressing whenever it may require it. This
means that LLVM never really needs an explicit addr32 prefix to
use 32-bit addressing in 16-bit mode.

Change-Id: Ia160d3f7da6653ea24c8229dc26f265e5f15aabb
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-02 15:21:21 +00:00
Kyösti Mälkki
6acaca7e40 AGESA: Remove separate f15rl
Change-Id: I18c62ad034249c5ad14e5d5e708b4f0d4bcbf400
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-31 16:28:55 +00:00
Edward O'Callaghan
4e2294b429 cpu/x86 asm: Just use the correct op suffix
LLVM AS doesn't support as much GNU junk extensions, data16/32
is almost never needed in truth if we just use the correct op
suffix. So do that here, fixes clang/llvm builds with the
integrated-as toggled on.

Change-Id: I6095d03d0289b418a49a10f135de5eb0e117cae0
Also-by: Damien Zammit <damien@zamaudio.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-31 15:29:52 +00:00
Kyösti Mälkki
5934be25fd AGESA: Drop Kconfig CPU_AMD_SOCKET_AM3R2
Never selected in our tree.

Change-Id: I5065903ebf74d281ecccaf53e0cc9fa24317e1cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-30 03:52:19 +00:00
Kyösti Mälkki
1203115077 AGESA: Remove Kconfig AMD_AGESA_FAMILY10
Never selected in our tree. The vendorcode source
for fam15 also includes fam10 support if required.

Change-Id: Ifff328ecdd8afa988f844b6fd631818b51bd5b5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28 14:38:29 +00:00
Kyösti Mälkki
8e0bc131c8 AGESA f15: Remove f10 references
Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.

Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-28 14:38:04 +00:00
Kyösti Mälkki
1438245334 AMD K8 fam10-15: Tidy up CAR stack switch
Return to empty stack before making the switch.

Change-Id: I6d6f633933fac5bc08d9542c371715f737fb42cf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:25:15 +00:00
Kyösti Mälkki
90e07b460c AMD K8 fam10-15: Consolidate post_cache_as_ram call
Change-Id: I5e7890aafbc8c80716ee49690e306482a482a863
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20573
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-08-22 20:24:38 +00:00
Kyösti Mälkki
b98391c0ee AMD K8 fam10-15: Tidy up CAR disable
Avoid conflicting disable_cache_as_ram() declaration and tidy
up include for inlined function.

Change-Id: Iba77c711f5eb023566b7d8ba148583948661bc99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-22 20:24:31 +00:00
Kyösti Mälkki
e09cd1b787 arch/x86: Sanity checking on HAVE_SMI_HANDLER
Fail at build-time if one of the following happens:

Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.

Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.

Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-08-19 15:34:48 +00:00
Kyösti Mälkki
a9450081cf intel/smm/gen1: Backup default SMM area
Fix low memory corruption on S3 resume path.
Affected platforms were sandy/ivybridge.

Change-Id: I7379e7396b61ee4dc2438276d530feffaa1bc8f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21100
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-08-19 15:32:18 +00:00
Kyösti Mälkki
2e50142f62 i82801dx/gx/ix/jx: Add low-memory backup for S3 path
SMM relocation code overwrite low memory owned by OS.

Change-Id: Ifa3d28bed3d3db65b0707bde62ae2b424a231f1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19405
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19 15:31:51 +00:00
Kyösti Mälkki
0cc2ce4327 arch/x86: Clean up CONFIG_SMP and MAX_CPUS test
Change-Id: I7c138758707f87c0d7a827b6887c7752d3714cde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-19 15:30:51 +00:00
Kyösti Mälkki
ff284f6566 arch/x86: Fix ugly NEED_LAPIC use
Change-Id: I2d6fdfd0465fe5f558daa04c6f980f7226596b55
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-19 15:30:40 +00:00
Nico Huber
0f2dd1eff9 include/device: Split i2c.h into three
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.

* `i2c.h`        - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
                   per board, devicetree independent I2C interface
* `i2c_bus.h`    - will become the devicetree compatible interface for
                   native I2C (e.g. non-SMBus) controllers

Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-18 15:33:29 +00:00
Kyösti Mälkki
111926a166 AGESA: Cleanup ACPI S3 support
Due to low-memory corruptions S3 support has now been
(at least temporarily) removed from AGESA platfroms.
Should we bring it back one day, CAR teardown on S3 path
will happen with an empty stack so ugly backup/recovery
of the stack will no longer be used.

If S3 feature is brought back, resume path code for FCH
will also see partial rewrite and agesawrapper.c file
will not be part of that.

Change-Id: Ib38c04d0e74f600e0b719940d5e2530f4c726cfd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-16 22:06:51 +00:00
Nico Huber
029dfff30c i2c: Move to Linux like struct i2c_msg
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.

Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.

The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.

Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.

Patched with Coccinelle using the clumsy spatch below and some manual
changes:

* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.

    @@ @@
    -struct i2c_seg
    +struct i2c_msg

    @@ identifier msg; expression e; @@
    (
     struct i2c_msg msg = {
    -    .read = 0,
    +    .flags = 0,
     };
    |
     struct i2c_msg msg = {
    -    .read = 1,
    +    .flags = I2C_M_RD,
     };
    |
     struct i2c_msg msg = {
    -    .chip = e,
    +    .slave = e,
     };
    )

    @@ struct i2c_msg msg; statement S1, S2; @@
    (
    -if (msg.read)
    +if (msg.flags & I2C_M_RD)
     S1 else S2
    |
    -if (msg.read)
    +if (msg.flags & I2C_M_RD)
     S1
    )

    @@ struct i2c_msg *msg; statement S1, S2; @@
    (
    -if (msg->read)
    +if (msg->flags & I2C_M_RD)
     S1 else S2
    |
    -if (msg->read)
    +if (msg->flags & I2C_M_RD)
     S1
    )

    @@ struct i2c_msg msg; expression e; @@
    (
    -msg.read = 0;
    +msg.flags = 0;
    |
    -msg.read = 1;
    +msg.flags = I2C_M_RD;
    |
    -msg.read = e;
    +msg.flags = e ? I2C_M_RD : 0;
    |
    -!!(msg.read)
    +(msg.flags & I2C_M_RD)
    |
    -(msg.read)
    +(msg.flags & I2C_M_RD)
    )

    @@ struct i2c_msg *msg; expression e; @@
    (
    -msg->read = 0;
    +msg->flags = 0;
    |
    -msg->read = 1;
    +msg->flags = I2C_M_RD;
    |
    -msg->read = e;
    +msg->flags = e ? I2C_M_RD : 0;
    |
    -!!(msg->read)
    +(msg->flags & I2C_M_RD)
    |
    -(msg->read)
    +(msg->flags & I2C_M_RD)
    )

    @@ struct i2c_msg msg; @@
    -msg.chip
    +msg.slave

    @@ struct i2c_msg *msg; expression e; @@
    -msg[e].chip
    +msg[e].slave

    @ slave disable ptr_to_array @ struct i2c_msg *msg; @@
    -msg->chip
    +msg->slave

Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-14 18:07:30 +00:00
Kyösti Mälkki
903ce25040 binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpart
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 05:11:04 +00:00
Kyösti Mälkki
6e37b0acb6 binaryPI: Enable EARLY_CBMEM_INIT
Also moves postcar stack to CBMEM.

Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02 04:57:07 +00:00
Kyösti Mälkki
7369e83de1 AGESA: Add romstage timestamps
Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.

Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:51:02 +00:00
Kyösti Mälkki
fb32be4090 AGESA: Implement EARLY_CBMEM_INIT
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT.
This does not apply to family12 and family14 just yet, as
they do invalidate without write-back on CAR teardown.

Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:50:33 +00:00
Kyösti Mälkki
21e609c1c9 AGESA: Move romstage-ramstage splitline
In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.

As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.

Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:48:20 +00:00
Kyösti Mälkki
ed8d2777f8 AGESA binaryPI: Unify agesawrapper header
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:48:06 +00:00
Kyösti Mälkki
a3d644fcd1 AGESA: Consolidate platform_once() call
Change-Id: I13d8df330db925b2eced7c123ca9926fb259646d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20621
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02 04:46:58 +00:00
Kyösti Mälkki
b0931d3d10 AGESA: Consolidate early_all_cores() call
Change-Id: I7c3af493b9189bb75a58eb322646694b5a712745
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:46:36 +00:00
Kyösti Mälkki
28c4d2f7e0 AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:46:29 +00:00
Evelyn Huang
284409fd8c src/cpu/amd/quadcore: Fix checkpatch errors/warnings
Fix over 80 character line warnings, unncessary braces for single
statement blocks warnings, include space before and after =, <, >
warnings, spaces after open parantheses warnings

Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01 23:02:11 +00:00
Evelyn Huang
0182aea283 cpu/amd/pi: Fix checkpatch warnings and errors
Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi

Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01 23:01:56 +00:00
Kyösti Mälkki
c27daff542 binaryPI: Drop remains of ACPI S3 on FCH
Never reached and actual code was already wiped out.

Change-Id: Ic17cbc56e83d23e228e23578357843ac9cd77eda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20623
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-29 07:59:54 +00:00
Martin Roth
e5f2d4c44c src/cpu: Fix checkpatch warning: no spaces at the start of a line
Change-Id: Iabdaaaee49e8c5cead304cda66412aa36a2ffd19
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-07-28 16:24:49 +00:00
Martin Roth
467a87abce Fix files with multiple newlines at the end.
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24 15:08:08 +00:00
Martin Roth
b137c13e57 I82801JX: Add IS_ENABLED around config options
This chipset was just added and had a few places that needed to be
fixed.

Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-21 17:00:01 +00:00
Arthur Heymans
349e08535a sb/intel/i82801jx: Add correct PCI ids and change names
Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-21 15:44:19 +00:00
Marshall Dawson
fb66e81e6c x86/lapic/secondary.S: Align stack for _secondary_start
At a process _start, the stack is expected to be aligned to a
16-byte boundary.  Upon entry to any function the stack frame
must have the end of any arguments also aligned.  In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).

Align the stack down inside _secondary_start and preserve proper
alignment for the call to secondary_cpu_init.

Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.

1) http://wiki.osdev.org/System_V_ABI
   See "Initial Stack and Register State" and "The Stack Frame"
   in the supplements.

BUG=chrome-os-partner:62841664

Change-Id: I72b7a474013e5caf67aedfabeb8d8d2553499b73
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-20 15:34:21 +00:00
Kyösti Mälkki
bebd766f16 binaryPI: Disable CAR with empty stack
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.

While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.

We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.

Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-17 19:31:09 +00:00
Kyösti Mälkki
044dec27b4 binaryPI: Switch to agesa/heapmanager.c
Essentially squashes following commits from AGESA side.

45ff9cb AGESA: Reduce typecasting in heapmanager calls
bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly
4240277 AGESA: Adjust heap location for S3 resume path
424c639 AGESA: Refactor S3 support functions
50e6daf AGESA: Log heap initialisation
da74041 AGESA: Move heap allocator declarations
c74b53f AGESA: Reduce SPI use by 24kB for S3 support
b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts
f728408 AGESA: Split S3 backup in CBMEM
82fbda7 AGESA: Use same HeapManager for all BiosCallOuts

Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-17 19:25:57 +00:00
Kyösti Mälkki
fec6fa799c vendorcode/amd/agesa: Tidy up gcccar.inc
Change register preservations and fix comments about register
usage accordingly. Do this to avoid use of %mm0-2 registers inside
macros defined in gcccar.inc, as future implementation of
C_BOOTBLOCK_ENVIRONMENT will use them as well.

Adjust caller side accordingly.

Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-07-15 16:10:19 +00:00
Kyösti Mälkki
2a7fbea3f1 K8: Fix indirect includes
Change-Id: I370285aa52776170a32b6dd36c0eef74eea9400c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-14 07:23:18 +00:00
Martin Roth
0fa92b31b0 src/cpu: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-13 23:55:25 +00:00
Stefan Reinauer
6a00113de8 Rename __attribute__((packed)) --> __packed
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))

Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13 19:45:59 +00:00
Kyösti Mälkki
fa2786a010 binaryPI: Drop non-soc stoneyridge trees
These sources are no longer part of build-tests and transition
to soc/ appears to be completed.

Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-07-12 03:34:46 +00:00
Ryan Salsamendi
70c27de571 cpu/intel/haswell: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow. Left
shifting an int where the right operand is >= the width of the type
is undefined. Add UL suffix since it's safe for unsigned types.

Change-Id: Ieacf83d052bf4abfad639ef8e592bd8de17d16e6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-07-06 20:19:25 +00:00
Ryan Salsamendi
312b23522a cpu/x86/name: Fix undefined behavior
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
Remove unnecessary memset().

Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-07-03 17:15:28 +00:00
Martin Roth
ffdee287df cpu/intel: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:42 +00:00
Martin Roth
5f46af6325 cpu/amd: add IS_ENABLED() around Kconfig symbol references
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.

Change-Id: I9f4155285529ec28e826637a61436478f648704c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-28 17:48:34 +00:00
Arthur Heymans
3b633bbf1d cpu/intel/pineview: Include speedstep
Needed to generate cpu entries.

Change-Id: Ia3f5137c7642bb9f79562cc9d6e6881aca749179
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:48:41 +00:00
Elyes HAOUAS
168ef399c4 cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:23:32 +00:00
Stefan Reinauer
8d29dd1258 vendorcode/amd: Unify Porting.h across all targets
This requires to also unify the calling convention for
AGESA functions from
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
 AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)

On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.

Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-06-27 17:35:39 +00:00
Aaron Durbin
8ade68a270 cpu/x86/smm: allow SSE instructions in SMM modules
If SSE instructions are enabled in the build assume the SMM
modules are compiled with SSE instructions. As such enable
the SSE instructions in SMM mode by setting up the cr4 register.
In addition, provide a place to save and restore the SSE state
in both the relocation handler and permanent handler.

Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-06-27 16:14:15 +00:00
Elyes HAOUAS
80d11b2d58 cpu/allwinner/a10/clock.h: Add missing bracket
Code checked manually

Change-Id: I92f0b5d47c60c259171c4db90fb5003f4eb8580b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-22 16:05:28 +00:00