Bit 18 of MSR_POWER_CTL is documented as reserved, but we're setting it on
Haswell in order to enable EPB. It seems to work on SKL/KBL as well, so
do it there too.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: I83da1a57a04dac206cc67f2c256d0c102965abc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.
BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
2. Verify the MSR PL1 limitation is set correctly.
Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for SKL and KBL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase AP timeout limit for sgx_configure function. As per debug log
sgx_configure was not successful on all cores with given timeout value.
TEST=Ensures no timeout error in AP function execution.
Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In an attempt at consolidation, commit 0a203d1 [1] introduced
an additional read/write of the MISC_ENABLE msr, as well a bug
which nullified the setting of Intel SpeedStep by inserting said
read/write calls in between another set of read/write calls to the
same msr. Fix by reverting to previous (simpler) implementation.
[1] soc/intel/skylake: Use CPU common library code
https://review.coreboot.org/19566
Test: boot Linux on Librem13v2, read MISC_ENABLE msr and verify
SpeedStep bit correctly set based on devicetree setting.
Change-Id: Id2ac660bf8ea56d45e8c3f631a586b74106a6cc9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If given a value for PsysPl3 and/or Pl4, set the
appropriate MSR.
BUG=b:71594855
BRANCH=None
TEST=boot up and check MSRs in OS to make sure values are set as
expected. Test on Fizz, which will set these values in
mainboard.
Change-Id: Idbe04f48079b4fa3302d21acd065f2e4c53dd1ed
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
To remove chip.h dependency from SGX common code
- Create API soc_fill_sgx_param() and use it in sgx.c
- Implement same API for skylake/kabylake
- define sgx_param structure
Also include intelblocks/sgx.h instead of soc/msr.h
Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FIT is already loading microcode before CPU Reset. So, we need
not update the microcode again in RO FW in bootblock.
But we need to update in RW FW if there is any new ucode version.
So, added the update microcode function in get_microcode_info callback
before MP Init to make sure BSP is using the microcode from cbfs.
BUG=none
BRANCH=none
TEST=Build and Boot poppy
Change-Id: I5606563726c00974f00285acfa435cadc90a085e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20051
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If the boot media is memory mapped temporarily mark it as write
protect MTRR type so that memory-mapped accesses are faster.
Depthcharge payload loading was sped up by 75ms using this.
Change-Id: Ice217561bb01a43ba520ce51e03d81979f317343
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch implements SGX initialization steps in coreboot per Intel SGX
BWG rev 2.0.8 for Kaby Lake SoC. If enabled on a Kabylake device, SoC
capability and PRM (processor reserved memory) of desired size (needs to
be configured through PrmrrSize) are provisioned for later software
stack to use SGX (i.e., run SGX enclaves).
One issue is still puzzling and needs to be addressed: by calling
configure_sgx() in cpu_core_init() which is the per-thread function, SGX
is always failing for thread 0 but is successful for other 3 threads.
I had to call configure_sgx() again from soc_init_cpus() which is the
BSP-only function to make it enable on the BSP.
Another pending work is the implementation for the Owner Epoch update
which shall be added later.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified SGX activation is successful on all threads.
Change-Id: I8b64284875eae061fa8e7a01204d48d320a285a9
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: Macros with complex values should be enclosed in parentheses
ERROR: "foo * bar" should be "foo *bar"
ERROR: space required before the open parenthesis '('
ERROR: spaces required around that '=' (ctx:VxW)
WARNING: space prohibited between function name and open parenthesis '('
WARNING: storage class should be at the beginning of the declaration
WARNING: char * array declaration might be better as static const
WARNING: please, no space before tabs
WARNING: braces {} are not necessary for single statement blocks
WARNING: else is not generally useful after a break or return
WARNING: static const char * array should probably be static const char * const
TEST=Build for glados
Change-Id: Ic14ca3abd193cfe257504a55ab6b74782b26bf6d
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18868
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
