Currently, having a keyboard connected to the PS/2 controller of the
ASRock E350M1, after suspending and resuming the system, the keyboard
does not work anymore. A similar problem is documented in commit
448e3863 (drivers/pc80: Add PS/2 mouse presence detect) [1].
There is no reason to not disable the controller during resume. Also,
that way, the PS2 ASL method does not need to be overriden.
[1] https://review.coreboot.org/13165
TEST=Resume system, and notice PS/2 keyboard works.
Change-Id: I51dc446861120f80bc9ffc4cc54b86e317d99689
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Infineon TPM chip used on these platforms doesn't use an IRQ
line; the Linux kernel has been patched to work around this, but better
to remove it completely.
Test: boot linux on google/wolf,lulu,cyan without tpm_tis.interrupts=0
kernel parameter, observe no abnormal delays in boot or resume from S3.
Change-Id: Id510c73cfdc14b7f82b0cc695691b55423185a0b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
southbridge/amd/pi/hudson/imc.c procedure enable_imc_thermal_zone was
identified by coverity as having out of bounds access. Copies of the
procedure are present in southbridge/amd/agesa/hudson/imc.c and in
soc/amd/stoneyridge/imc.c. Fix the procedure in all 3 files.
Fixes coverity CID 1260807: Out-of-bounds read.
BUG=b:69835834
TEST=Build and platform boot to OS
Change-Id: Ic16edc607358b9a688151735e6fcb3393d3bce80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add coreboot support for CompuLab Intense-PC (Ivy Bridge)
Modifications:
- Memory SPDs have been fixed to detect both installed SODIMM modules
- Full-height Mini-PCIe slot defaults to PCIe mode
- mSATA can be chosen instead of mPCIe via Kconfig option ENABLE_MSATA
Tested (Xubuntu 17.10/Linux 4.13 where applicable):
- 2+2GB DDR3-1600 SODIMMs pass memtest
- 4+4GB DDR3-1600 SODIMMs pass memtest
- 4+8GB DDR3-1333 SODIMMs pass memtest
- 8+8GB DDR3-1333 SODIMMs pass memtest
- Booting via USB working (with no SATA HDD present)
- Booting to main SATA HDD working
- DisplayPort and HDMI output working for coreboot init (*requires* VGA BIOS)
- DisplayPort and HDMI dual-head working in Linux
- Mini-PCIe devices (half/full-height) detected in Linux
- mSATA working (when chosen using ENABLE_MSATA)
- Onboard Intel 82579 GbE working
- Secondary Realtek 8111 GbE working
- Rear eSATA ports working
- Onboard analog audio output working
- HDMI audio output working
- USB 3.0 working
- Suspend to RAM (S3) working, but not tested extensively
- Mini PCIe WiFi
- FACE module FM-4USB (4 USB 2.0 ports)
Disabled/unsupported:
- TPM (BTO option, not included in base config)
- FACE modules:
- FM-USB3 (USB 3.0/mSATA) NOT SUPPORTED/TESTED
- FM-SER (serial) NOT SUPPORTED/TESTED
- FM-XTDEU2/4 (LAN) NOT SUPPORTED/TESTED
- FM-XTDE4U2/4 (Quad LAN) NOT SUPPORTED/TESTED
- FM-XTDM2 (dual mPCIe) NOT SUPPORTED/TESTED
- FM-VC (video capture) NOT SUPPORTED/TESTED
- FM-POE (Quad LAN w/PoE) NOT SUPPORTED/TESTED
Not tested:
- RS-232
Product information:
http://www.fit-pc.com/web/products/intense-pc/
Change-Id: I741b0b2f87eb9147c375b405a5b6989a10c7ad0a
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I94d09a28bf1ea07a53cfa04c54752358bafca610
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Whenever there is a new EC event that could be wake-capable, notify
CREC device of this using notification value 0x2 i.e. device
wake. This allows Linux kernel to track active_count value correctly
for CREC device.
BUG=b:69118395
BRANCH=None
TEST=Verified on Soraka:
1. Put device into suspend
2. Wake up using mode change/lid open
3. Check that the active_count for GOOG0004 has increased
(cat wakeup_sources | grep GOOG0004)
Change-Id: I723f7f4e4c99e7a5b57c6296da66cf30cd413c27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the mainboard_spd_read function in romstage and call the variants
function. Grunt is the baseboard and has soldered down memory, so add
it for the default weak SPD functions and build the SPDs in cbfs.
Kahlee overrides the weak SPD function and falls back to the soc
I2C SPD functions.
BUG=b:67845441
TEST=Build and boot Kahlee.
Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change adds infrastructure to allow variants to define their own
camera.asl file.
- Poppy and soraka use the one provided by baseboard.
- Dummy file is added for nautilus since it does not have camera
support enabled yet.
TEST=Verified that DSDT table remains the same with and without this
change.
Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Refactor the mipi driver, so we can support dual mipi panel.
And pass the panel data from mainboard.c, that we can
support different panel with different board.
Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These values are specified as constant time periods but the PHY
configuration is in terms of the current lane byte clock so using
constant values guarantees that the timings will be outside the
specification with some display configurations.
Derive the necessary configuration from the byte clock in order to
ensure that the PHY configuration is correct.
Change-Id: I396029956730907a33babe39c6a171f2fcea9dcd
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch correct Feedback divider setting:
1. Due to the use of a "by 2 pre-scaler," the range of the
feedback multiplication Feedback divider is limited to even
division numbers, and Feedback divider must be greater than
12, less than 1000.
2. Make the previously configured Feedback divider(LSB)
factors effective
Change-Id: Ic7c5c59be1d00c65c3b17cb3c4bfba8d7459e960
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Accroding to datasheet, feedback divider register high value is only
4 bit, it currently uses 5 bit, so correct it.
Change-Id: I1fe9fc076b712f27407c5f2735b15e64fb55e72e
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.
Let's not waste time on the wake up ping when it is not necessary.
BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
generated only when the new coreboot stage or depthcharge start,
not on every SPI slave transaction.
Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SeaBIOS 1.11.0 was released on November 10th, 2017. Changes include
* Initial support for NVME drives
* Support for vga emulation over a serial port in SeaBIOS (sercon)
* Support for serial debugging using MMIO based serial ports
* Support for scsi devices with multiple LUNs
* Support for boot-to-boot persistent coreboot cbmem logs
* Improved coreboot vga (cbvga) mode setting compatibility
* Several bug fixes and code cleanups
See also https://www.seabios.org/Releases#SeaBIOS_1.11.0 and for all
details on the changes, use
git log --oneline rel-1.10.3..rel-1.11.0
in the SeaBIOS repository.
Change-Id: Ie46a526593177c5241fbd979c7fa1934478f7382
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/22429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add a CBSDK tool set template that can be used in edk2 simply by
appending $prefix/share/edk2config/tools_def.txt to Conf/tools_def.txt.
After that, build -t CBSDK uses the coreboot compilers, providing a more
predictable compiler choice.
Change-Id: I76b38c928b831ee6f31450aa0ad59b4f906f394d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
- Remove SI_ALL section. This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.
BUG=b:65497959, b:67035984
TEST=Build & boot kahlee
Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz
TEST= boot ok and the system can enter and resume from S3.
Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.
BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
are filled correctly && put system into S3 && sudo etherwake -i
eth0 $MAC to make sure the system could be woken up by WOL package.
Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With this implementation it's possible to detect the state
of bootguard in intel based systems. Currently it's WIP and
in a testphase. Handle it with care!
Changes done:
* Add support for reading msr
* Read ME firmware version
* Print bootguard state for ME > 9.1
* Make argument -s legacy
* Add argument -b for bootguard (and ME) dumping
* Add argument -m for ME dumping
* Opt out early if CPU is non Intel
Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/16328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clean the code to fix all errors and warnings.
No functional change.
Changes:
* Fix lines over 80chars
* Fix typos
* Restructure code to reduce indent level
* Move RCBA handling into own files
* Introduce helper functions for RCBA access
* Move GPL string into header
* Fix whitespace in macros
Change-Id: Ib8e3617ebb34c47959d6619dfbc7189045e6b8f7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
