With binutils 2.26 our memlayout ASSERT for mirrored SRAM regions
gets confused due to the lack of parentheses grouping the expressions.
This fixes the following issue:
LINK cbfs/fallback/bootblock.debug
mipsel-elf-ld.bfd: bootblock and gram_bootblock do not match!
mipsel-elf-ld.bfd: romstage and kseg0_romstage do not match!
Change-Id: Ib406e229b8a552d9ffc4538b55ee0269bfed62a8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14440
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
We never define B1_IMAGE or B2_IMAGE. These are about building
CIMx as separate binary modules, while coreboot builds these into
same romstage or ramstage module.
Change-Id: I9cfa3f0bff8332aff4b661d56d0e7b340a992992
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
The ME hangs, the lspci shows no memory and the linux kernel
tries to request irq 0 twice. After suspend-resume the linux
kernel warns about double used irq.
genirq: Flags mismatch irq 0. 00000080 (mei_me) vs. 00015a00 (timer)
mei_me 0000:00:16.0: request_threaded_irq failed: irq = 0.
dpm_run_callback(): pci_pm_resume+0x0/0xa0 returns -16
PM: Device 0000:00:16.0 failed to resume async: error -16
Change-Id: I56ef66388e58dddcfb858294ba274621c55fbef6
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14309
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Because the builders have the coreboot cross-compilers in their path,
the XGCCPATH variable needs to be set after building the new toolchain
before it will be used.
- Add $DEST/bin to $PATH if $DEST is set, add the default location
for toolchain builds otherwise. Because the jenkins build image puts
the tools in the path, we ca
- Add KEEP_SOURCES option to help speed up compilation (Slightly).
- Log .xcompile for verification that the right toolchain was used.
- Verify that test-toolchain passes.
Change-Id: I7c270dab94be7e8f801d527169767018a24986e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14231
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reorder drivers to fit src/drivers/[X]/[Y]/ scheme to make
them pluggable.
Also, fix up the following driver subdirectories by switching
to the src/drivers/[X]/[Y]/ scheme as these are hard requirements
for the main change:
* drivers/intel
* drivers/pc80
* drivers/dec
Change-Id: I455d3089a317181d5b99bf658df759ec728a5f6b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14047
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the coreboot makefiles repeatedly run git to try to set
the KERNELVERSION variable and to fetch the submodules. This happens
three times for every build. By exporting a variable, we can catch
this on recursive makes and not run each of these steps again.
Change-Id: I85ab867b40e80c36bd94d48510ffe3252c6cf93f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h.
barrier.h is present for x86, arm, and arm64, but not for mips. This
is generating a build error after enabling USB by default on libpayload.
I believe that this slipped through the buiders due to them not getting
cleaned fully. It was caught in the coverity scan and when setting up
a new build server.
Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14391
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
BIST result is already stored by arch/x86/bootblock_ctr0.S in
mm0. Also, eax does not contain BIST result by the time control
reaches bootblock_pre_c_entry. bootblock_crt0.S saves timestamp in mm2
which was being overwritten here. Thus, remove the saving of BIST
result from SoC code.
Change-Id: I65444689cf104c59c84574019f5daf82aab10bc7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14381
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Add Intel Broadwell-DE SOC and Camelback Mountain CRB to the list
Change-Id: I3f0c3ae8b38ecf3c3676fe497ade8b74ba94485d
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14382
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In northcluster.c, the set_resources member of struct device_operations
is set to NULL. That causes this message on the console:
PCI: 00:00.0 missing set_resources
Eliminate that warning by setting set_resources=DEVICE_NOOP.
Change-Id: I4c6c07fd40b180ca44fe67c4a4d07318df10c40f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14366
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
An unsigned enum expression is always strictly positive;
Comparison with '>= 0' is a tautology, hence remove it.
Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8207
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:
- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
per-board copy pasta)
Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
[pg: separated out from the combined commit that added both SoC and
board. Added board_info.txt that will be added downstream, too.]
Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/14279
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.
Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.
Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some ld versions seem to merge the .zeroptr section (NOLOAD, address 0)
with some debug sections (NOLOAD, address 0) which makes the build
explode when the debug sections are then stripped (including the zeroptr
symbol).
Just define zeroptr to be 0, no sections needed, to avoid this
"optimization".
Checked the objdump -dS of code using it that the accesses look sane.
Change-Id: Ia7cb3e5eae87076caf479d5ae9155a02f74b5663
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is a lot of generic code in the 8250 driver that should
be available for non-8250 systems with serial ports as well.
Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Store both the version number and git hash in the file name
when copying the buildgcc script to the destination directory.
Also, fix the quoting in the lines touched anyways, and move the
script to $TARGETDIR/share/
Change-Id: Ib37dc2be57ee7f0ae18a0b954f537f8b4c2db9d0
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14347
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Testing dev->chip == NULL when dev == NULL doesn't make sense (and gcc
thinks that's undefined behavior which should be rewarded with a trap).
Change-Id: I801ce3d6b791fdf96b23333432dee394aa2e2ddf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
