5b672d5954
soc/amd/common: Access ACPIMMIO via proper symbols
...
Using proper symbols for base addresses, it is possible to
only define the symbols for base addresses implemented for
the specific platform and executing stage.
Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-06-28 21:50:12 +00:00
b0ae42b5bb
AGESA fam14: Use AMD_ACPIMMIO_GPIO_BASE_100
...
Use the pre-defined constant address directly.
Change-Id: I29fbc82fffc69b864adb4ddbda1425db98e2e48a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-06-28 21:49:18 +00:00
19edbf640b
mb/google/zork: update DRAM SPD table for berknip
...
samsung-K4A8G165WC-BCWE_x1 # 0b0101
micron-MT40A1G16KD-062E-E_x2 # 0b0110
hynix-H5ANAG6NCMR-XNC_x2 # 0b0111
samsung-K4AAG165WA-BCWE_x2 # 0b1000
BUG=b:159418772
BRANCH=master
TEST=emerge-zork coreboot
Change-Id: I24b632c75d4a0660dc6beb88f135b546860d7079
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42814
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-28 21:48:55 +00:00
c746a748c4
smbios: Add option VPD_SMBIOS_VERSION that reads BIOS version from a VPD variable
...
If VPD_SMBIOS_VERSION is selected, it would read VPD_RO variable that can
override SMBIOS type 0 version.
One special scenario of using this feature is to assign a BIOS version to
a coreboot image without the need to rebuild from source.
VPD_SMBIOS_VERSION default is n.
Tested=On OCP Delta Lake, dmidecode -t 0 can see the version being updated
from VPD.
Change-Id: Iee62ed900095001ffac225fc629b3f2f52045e30
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: insomniac <insomniac@slackware.it >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2020-06-28 21:48:38 +00:00
360684b41a
soc/intel/common: add TCC activation functionality
...
This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value. Also, cleanup local functions
from previous intel soc specific code base like for apollolake, broadwell,
skylake and cannonlake.
BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.
Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-06-28 21:47:52 +00:00
5270ce133e
mb/google/zork: update telemetry settings for berknip
...
update telemetry to improve the performance.
BUG=b:154879805
BRANCH=master
TEST=emerge-zork coreboot
verify by Stardust test
Change-Id: Iae5486cf2ee26b3d8e6124edfff4fe2d1fbe211e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42817
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-28 21:47:35 +00:00
3c9b35f8c3
mb/google/zork: add G2 TS support for berknip
...
Add G2 GTCH7503 HID TS support
BUG=b:159510906
BRANCH=master
TEST=emerge-zork coreboot
boot with G2 TS, make sure G2 TS is functional
Change-Id: Id9ed5fc768459edc4660ddd6fbffb0b1973ce6d1
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-06-28 21:47:27 +00:00
7c606eca05
mb/google/zork: update telemetry settings for morphius
...
update telemetry to improve the performance.
BUG=b:154863613
BRANCH=master
TEST=emerge-zork coreboot
Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-06-28 21:47:06 +00:00
b721f045e3
mb/google/zork: update DRAM SPD table for morphius
...
Add Samsung K4A8G165WC-BCWE x2
BUG=b:159418770
BRANCH=master
TEST=emerge-zork coreboot
Change-Id: I200a1074d3c9fe79a8a2c69f42b0612e745f36f5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-06-28 21:46:59 +00:00
858890765e
mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL support
...
Add Samsung K4F8E3S4HD-MGCL DRAM support.
DRAMID: 0x8
BUG=b:145094527
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-06-28 21:46:01 +00:00
104c3e5f9b
Makefile.inc: Simplify fsp submodule check
...
TEST=Building Asrock H110M using FSP from repo updates the submodule.
Change-Id: I25023af88d878353a04db456009249da67e41521
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2020-06-28 21:45:47 +00:00
d4698d94af
soc/xeon_sp/cpx: Define MSR PPIN related registers
...
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP DeltaLake with change
https://review.coreboot.org/c/coreboot/+/40308/
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Change-Id: I87134b2e98c9b0c031be9375b75a2aa1284ae9bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com >
2020-06-28 21:44:27 +00:00
db654eae79
drivers/ipmi: Read more FRU data fields for Product and Board Info
...
Tested on OCP Tioga Pass
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com >
Change-Id: Ib05fdb34b2b324b6eb766de15727668ce91d2844
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40522
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Jonathan Zhang <jonzhang@fb.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-28 21:43:59 +00:00
ba26aa8981
mb/google/faffy: Enable USB2 port6
...
Due to faffy has PL-2303 connect to USB2 port6(count from port0),
needs to enable it.
BUG=b:159760559
BRANCH=None
TEST=emerge-puff coreboot chromeos-bootimage
boot on puff board
Change-Id: Icc805757b043e7fac4d05188cbf2f9c9c56c2a2e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
2020-06-28 21:43:45 +00:00
346f391642
mb/amd/mandolin: factor out eMMC GPIO pin mux setup
...
This also makes the calling of the eMMC GPIO mux setup function
conditional on PICASSO_LPC_IOMUX instead of AMD_LPC_DEBUG_CARD which
only makes the selection of PICASSO_LPC_IOMUX user-configurable.
Change-Id: Ic49a668f82fbc1b851c07d312b543d2889fe4734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-06-28 14:20:11 +00:00
664ba9767d
mb/amd/mandolin: factor out port descriptors from mainboard.c
...
Change-Id: Ia2101cc0bae0d68cea1954424d18833aa22670c6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42784
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-28 14:17:34 +00:00
42b0e8f438
soc/amd/picasso/soc_util: rework reduced I/O chip detection
...
Both Dali and Pollock chips have less PCIe, USB3 and DisplayPort
connectivity. While Dali can either be fused-down PCO or RV2 silicon,
Pollock is always RV2 silicon.
Since we have all boards using this code in tree right now,
soc_is_dali() can be renamed and generalized to soc_is_reduced_io_sku().
Change-Id: I9eb57595da6f806305552128b0c077ceeb7c4661
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42833
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Rob Barnes <robbarnes@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-28 14:16:36 +00:00
fa8b75fb17
gpio_keys: Allow boards to configure different wakeup routes
...
This change allows mainboard to configure different wakeup routes that
can be used by a GPIO key:
1. SCI: This is selected when SCI route is used to wake the system. It
results in _PRW property being exposed in ACPI tables.
2. GPIO IRQ: This is selected when GPIO controller wake is used to
wake the system. It is typically used when the input signal is not
dual routed and the GPIO controller block is not capable of applying
filters for IRQ and wake separately. In this case, _PRW is not exposed
in ACPI tables for the key device.
3. Disabled: No wakeup supported.
Based on these wakeup routes, gpio_keys_add_child_node() is updated to
expose _PRW and _DSD properties for wakeup appropriately.
Additionally, the change updates mainboards that were already using
gpio_keys to set wakeup_route attribute correctly and renames "wake"
to "wake_gpe" to make the usage clear.
BUG=b:159942427
Change-Id: Ib32b866b5f0ca559ed680b46218454bdfd8c6457
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-06-28 05:22:41 +00:00
490473edec
sb/intel/i82801jx: Use pmutil.h definitions
...
Also drop now-redundant definitions and include headers where needed.
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.
Change-Id: I2fb46bb04d96df5e8261f49e0fd4d88eedca6084
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42659
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 23:37:30 +00:00
e1a616cf99
sb/intel/i82801ix: Use pmutil.h definitions
...
Also drop now-redundant definitions and include headers where needed.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: I3ddd133a4e81a7f6ce9c33ce227b40006a0d1850
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42658
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 23:37:19 +00:00
b60aeca26c
sb/intel/i82801jx: Drop p_cnt_throttling_supported
...
The three mainboards using this southbridge do not support it.
Change-Id: I006f1ec26c40f7e2dfc2ddedb017278455368bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42655
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 23:36:34 +00:00
547fe82cd0
sb/intel/i82801ix/fadt.c: Use pmutil.h definitions
...
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ib4cdeaaaf75818fff21acb628d198781b07aec80
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42654
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 23:36:21 +00:00
7c86f4a822
sb/intel/i82801jx/fadt.c: Use pmutil.h definitions
...
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.
Change-Id: I572a9da0cba5d23c48c4cb06de4bb75f65f5b0b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: ron minnich <rminnich@gmail.com >
2020-06-27 23:36:10 +00:00
f4bbea0f79
sb/intel/i82801gx/fadt.c: Align with i82801ix
...
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I930de15a6746936fa4a8f6db280b5ac60176c836
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-06-27 17:39:24 +00:00
741508bb3e
sb/intel/i82801gx/fadt.c: Reorder statements
...
Change the order of the assignments to match that of i82801ix. This
changes the binary but the effective result should be the same.
Change-Id: Id720fce40e751295e629585d34017f10af2b5c7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42651
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 17:38:20 +00:00
3fc2dc444e
sb/intel/i82801gx: Move acpi_fill_fadt to fadt.c
...
At least i82801ix and i82801jx do this.
Change-Id: I7ff2459d82eb7933ed80180a69f0f323b8ecd25f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-06-27 17:38:11 +00:00
9e5b432ef9
sb/intel/i82801jx/fadt.c: Align with i82801ix
...
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.
Change-Id: I13b972440459a62777ee2a4688d1d8af147d8921
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2020-06-27 17:37:23 +00:00
9cf2abd6f9
sb/intel/i82801jx/fadt.c: Reorder statements
...
Change the order of the assignments to match that of i82801ix. This
changes the binary but the effective result should be the same.
Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2020-06-27 17:37:05 +00:00
dd7fa543c5
sb/intel/i82801jx: Move acpi_fill_fadt to fadt.c
...
At least i82801ix does this.
Change-Id: Ic555ab17c2eca0399938d2842ca51628899c1544
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42637
Reviewed-by: Christian Walter <christian.walter@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 17:36:39 +00:00
22a6d11a54
mb/emulation/qemu-q35: Use common early SPI code
...
Tested, it still boots. It is unknown whether this has any effect on
emulated hardware, which is most likely not emulating SPI transfers.
Change-Id: I44397c46dc0715697ca8680f418888804e4ea7e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:31:13 +00:00
5403423656
soc/intel/broadwell: Use common early SPI code
...
Change-Id: Ifd0e8e6d8169a762a4d17839c3fd7b7e5493a344
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:31:02 +00:00
4c7ef81a23
sb/intel/lynxpoint: Use common early SPI code
...
Change-Id: I6c6fbed077d2f169736aee77af3783c847cf3a06
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:30:48 +00:00
8caa53133f
sb/intel/ibexpeak: Use common early SPI code
...
Change-Id: Ib8cba1ae4fc269c925418965acf6956c1bfe0f79
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:30:37 +00:00
40783f2862
sb/intel/i82801jx: Use common early SPI code
...
Change-Id: If9efbde5939913b67852b377dd84cd4de1ec2718
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:29:48 +00:00
298aa98b81
sb/intel/i82801ix: Use common early SPI code
...
Change-Id: Iafcf7aecb20b4c8be79fa562ff267fd54f672862
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:29:33 +00:00
cf39f89fd9
sb/intel/i82801gx: Use common early SPI code
...
Change-Id: I44de4698d062508dd24f37b37014e09d95726c71
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:29:23 +00:00
c9ee2c0323
sb/intel/bd82x6x: Use common early SPI code
...
Change-Id: If4843e93c993ed2de60b2b6064c2c9e98637ce9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42661
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-27 17:29:02 +00:00
fc7bc54e34
sb/intel/common: Add early SPI code
...
All Intel southbridges with SPI perform this write. Put it inside a
function in common code. Use a different name to avoid a name clash.
As it is only one statement, make it inline so that it can be defined
on the header itself. It is only called once per southbridge anyway.
Change-Id: I3c284d6cffd22949d50b4c4f9846ceaef38d7cda
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-27 17:28:53 +00:00
f183626b22
Revert "Mushu: Enable PCIe 1d.4 to enable dgpu"
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This reverts commit 1408798637shchen@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
2020-06-26 21:25:32 +00:00
4ab5ce1430
soc/rockchip: Use (Q) instead of @
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This way make V=1 will tell you what it's actually doing.
Change-Id: I096bc2419e47a0b2a2454a792059464b27158cd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42818
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-26 21:13:33 +00:00
97716b18d7
mb/mandolin/devicetree: clarify that Ethernet devices are internal MACs
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Change-Id: Ib7d696f4cc8f5fdcdf45e271b36664d085eb16d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42834
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-26 20:47:18 +00:00
b212b67df1
mb/amd/mandolin/devicetree: disable unused internal ethernet controllers
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Change-Id: Id4c7ec02f37b35bbc36d40bb937b962cc6413d17
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42782
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-26 20:46:15 +00:00
88e54e38d4
Fix up Docker paths to match jenkins nomenclature
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Jenkins is calling its build nodes "agent". Reflect that in
the path names we use in configuration.
Change-Id: I88a4d3d32a565ade768e3de6428f46d355bedfb2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42819
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-26 18:56:48 +00:00
ad977efa23
mb/google/zork/Kconfig: remove unused option IRQ_SLOT_COUNT
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That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.
Change-Id: Ib5839a42f5133f5f84e1e1e4e587801b916ca571
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2020-06-26 16:14:47 +00:00
3d53d5397f
mb/amd/mandolin/devicetree: add comment about chip behind GPP bridge 3
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Change-Id: Ie1fcfb18a3ccf08c62210eec07d8965696f11da9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-06-26 16:08:12 +00:00
23cdcb8bef
mainboard/prodrive/hermes: Enable EIST in DeviceTree
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Enable EIST option in the devicetree in order to make Windows aware of
using Intel CPU Turbo Technology.
Change-Id: Ied3d7e934fcab2d5d491573245d68d392df5ba34
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-06-26 05:35:43 +00:00
469dda3339
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
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Currently, Reset Power Cycle Duration is set with default value (4s).
This adds around ~5 seconds of delay during power cycle or global reset.
So, this patch sets PchPmPwrCycDur (Reset Power Cycle Duration) to 1s
to minimize the delay.
Delay with Power Cycle or Global Reset:
Existing behaviour:
S0->S5 -> [ ~5 seconds delay ] -> S5->S0
With the patch:
S0->S5 -> [ ~2 seconds delay ] -> S5->S0
Also, correct the comment mentioned for PchPmSlpAMinAssert.
The value(3) defined for PchPmSlpAMinAssert triggers signal assertion width
to 98ms not 2s.
Test=Verified on Hatch and Puff boards
BUG=b:158634281
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42441
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com >
Reviewed-by: V Sowmya <v.sowmya@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-06-26 00:15:04 +00:00
154625bcb2
mb/google/volteer: Enable HECI interface
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This is to enable Intel ME communication interface HECI1 by
devicetree for PAVP with CSE Lite.
BUG=b:159615125
TEST=Build and boot volteer. Run lspci and check pcie device
00:16.0 Communication controller: Intel Corporation Device a0e0
Change-Id: I68eb51c6a0af77982c060767993265764a2bc926
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-06-25 20:58:55 +00:00
bc6aa222a6
mb/amd/mandolin: remove unused option IRQ_SLOT_COUNT
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That option is only relevant if the boards selects HAVE_PIRQ_TABLE which
it doesn't.
Change-Id: I76c098c7029ed9d797f6c4fb016eaa18854fadd3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-06-25 20:36:11 +00:00
cd36c52d78
mb/amd/mandolin: add missing Kconfig type to CBFS_SIZE option
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Change-Id: Ia4226537d17bb3732086980fb4e8de6bd1eaedbb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-06-25 20:36:01 +00:00
