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20 Commits

Author SHA1 Message Date
Angel Pons
aa4cd73409 util/inteltool: Add 9 series PCH support 
Add the PCI device IDs for 9 series PCHs.

Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-10-08 21:03:58 +00:00
Angel Pons
65adc70165 util/inteltool: Add ICH10D PCI ID 
Add the PCI device ID for the ICH10D southbridge. While we're at it,
also fix up whitespace in inteltool.h of an adjacent definition.

Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2021-11-19 13:54:48 +00:00
Idwer Vollering
66dcda9e15 util/inteltool: add PCI ID for ICH10DO 
Change-Id: I3561679ef50f4c094d2503539074c957f759ecef
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-09 21:54:33 +00:00
Michael Niewöhner
10d522133e util/inteltool: use read* macros instead of pointers 
Switch to using read* macros instead of pointers.

Change-Id: I1fe54b496a5998597b79cdd7108f3a4075744a78
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-03-21 22:12:10 +00:00
Michael Niewöhner
d3dab12244 util/inteltool: spi: add a bunch of missing chipsets to print_bioscntl 
Add a bunch of missing chipsets to print_bioscntl.

Change-Id: I96c010a1d64dcf5296f78a6decd1a218aba4b04f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-03-17 01:00:32 +00:00
Elyes HAOUAS
6dc9d0352e treewide: capitalize 'BIOS' 
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.

Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-02-17 20:11:24 +00:00
Jacob Garber
6faccd1f00 util/inteltool: Make internal functions static 
None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-07-07 20:23:42 +00:00
Felix Singer
0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs 
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-05-06 10:38:49 +00:00
Matthew Garrett
2bf28e52ee util/inteltool: Add support for Sunrise Point LP 
Used documents:
334658 (Sunrise Point-LP I/O datasheet vol. 1)
334659 (Sunrise Point-LP I/O datasheet vol. 2)
332690 (Sunrise Point I/O datasheet vol. 1)

Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/28623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2018-12-28 22:31:54 +00:00
qeed
b775a62bb9 inteltool: Add PCI IDs for the C220 PCH series 
Adds missing PCI IDs to allow tool to dump the
C220 PCH (8 series) southbridge.

Intel Document 328904 is the datasheet for this PCH.

Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan@gmail.com>
Reviewed-on: https://review.coreboot.org/27168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2018-06-21 17:39:48 +00:00
Arthur Heymans
485c0ad078 inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI 
Tested to display the register content correctly on a Lenovo Thinkpad
X220.

Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2018-02-06 16:11:45 +00:00
Arthur Heymans
921fa84f9e inteltool: Fix displaying 64bit spi registers 
The registers were taken from the wrong addess since the spibar offset
was not added to it.

This also fixes the endianness.

Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-02-06 16:09:03 +00:00
Youness Alaoui
1244a510f1 util/inteltool: Add support for Wildcat Point-LP Premium 
The Wildcat Point-LP Premium is handled the same as the Wildcat Point-LP,
but it wasn't supported by inteltool.

Change-Id: I694514e1963f074582a3f5f81d63c20e7fa49189
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19445
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2017-05-01 00:43:52 +02:00
Arthur Heymans
026f7df763 util/inteltool: Add ICH10 (Consumer Base) support 
Reuses ICH10R functions.

TESTED on Intel DG43GT (Not supported by coreboot)

Change-Id: If9ae8ba8b95e3a7bf6596ae639eb8cafab583298
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19232
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2017-04-15 20:06:08 +02:00
Arthur Heymans
7ff4fe1237 util/inteltool: Add ICH6-10 to BIOS_CNTL list 
Without this change inteltool cannot read BIOS_CNTL values nor can it
read the SPIBAR values.

Change-Id: I9ff16e060aca66e3cb11c8315a6843ccecd1d3c2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2017-01-03 17:40:34 +01:00
Arthur Heymans
a5798a9b8f util/inteltool: Fix ICH SPIBAR registers 
The ICH7 SPIBAR offset and registers are different from later
generation.
ICH8 has a different offset from later generation.
ICH6 has no SPI controller.

Change-Id: I7691bce619089b15805114047bcb1fd121a5722b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2017-01-03 17:40:11 +01:00
Elyes HAOUAS
52648623e0 Remove empty lines at end of file 
Used command line to remove empty lines at end of file:
find . -type f -exec sed -i -e :a -e '/^\n*$/{$d;N;};/\n$/ba' {} \;

Change-Id: I816ac9666b6dbb7c7e47843672f0d5cc499766a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/10446
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2015-06-08 00:55:07 +02:00
Matt DeVillier
5b667df135 util/inteltool: add Broadwell-U support 
add handling of PCI IDs for Broadwell-U/Wildcat Point LP,
using same functions as Haswell-U/Lynx Point LP

Change-Id: I1094cbdace3c73f0f85c2e27c676b877b1a04bfe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2015-05-16 08:14:21 +02:00
Lubomir Rintel
2a13bad8df inteltool: add ICH8M-E support 
Tested on a Lenovo X61.

Change-Id: I047f5a029d9be9fe6a000e2b45be44c7f14b33d7
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: http://review.coreboot.org/8568
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2015-03-26 03:33:46 +01:00
Alexander Couzens
aa3dd5d5db inteltool: add -s to dump spi bar and bios_cntl registers 
Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8049
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2015-01-08 17:49:58 +01:00