The default GPIO values for camera power were set as 1 so the LED was
turned on by default when the board is powered on.
This status is kept until the camera is probed then being turned off.
So the LED is turned on for a few seconds during the boot up.
By setting the default power to 0, the LED is lit only when camera
is turned on for probing and this should be just a blink.
BUG=b:167635396
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it is not lit more than 0.5 seconds.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cameras
There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c
device can support driver probe without power up the device.
In order to support this, need add coreboot add
"i2c-allow-low-power-probe" property.
BUG=b:169058784
BRANCH=none
TEST=Build and boot volteer board. Monitor camera privacy LED
and check it blinks. It should not blink.
Signed-off-by: Daniel Kang <daniel.h.kang@intel.com>
Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This fixes non-emulation platforms as those are using 32bit code
after the bootblock_crt0 entry, like setting up CAR and updating
microcode, which isn't yet converted to support long mode.
This is a noop for the only supported x86_64 platform and all
x86_32 platforms.
Change-Id: I45e56ed8db9a44c00cd61e962bb82f27926eb23f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change allows treating the PMC as a 'hidden' PCI device on
JasperLake, so that the MMIO & I/O resources can be exposed as
belonging to this device, instead of the system agent and LPC/eSPI.
Original patch for jasperlake SoC here:
CB:42018
This change was missing for JasperLake rvp board.
TEST=Checked PMC init function is called and also checked PCI resource
for PMC device 1f.2.
Change-Id: I7531d32c62d3f9735938f744f2892ab9c9bebddf
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Using bincfg, generate Intel 82579LM GBE region firmware.
* Intel 82579LM is used in Lenovo models including x220 and x230.
* PXE is disabled.
* Intel 82579V variant could be generated with a few modifications to
set. Noted in set file comments.
Change-Id: I377cbe2f77f2aef39f452dc6511a0ea6b2015963
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
They should be tuned per board to get the best signal and boot time.
This fixes the HS400 preset, so it's correctly set to A. It also changes
the SDR50 and DDR50 presets to B. We can't boot correctly when DDR50 is
set to A.
I chose 1 as the init kHz value since that's what depthcharge uses to
calculate the init clock.
BUG=b:159823235
TEST=Boot Ezkinil and dump SDHCI preset registers.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie2f3497b65d771820ab1a803fec73265547f8906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows passing in the presets to FSP.
I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add ACPI name for CSTACK. The name is PC00 to match with ACPI table
generated.
The PCIe domain has multiple PCIe stacks. devicetree.cb at the moment
does not support multiple PCIe stacks, eg. IIO stacks. For now, assign
the name to PCIe domain. In future, the name needs to be assigned to
CSTACK.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I24a6f29734452426218419cdcf66702edde96f46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add ACPI name for LPC device. The name matches with what is in
soc/intel/common/block/acpi/acpi/lpc.asl.
Since several Intel SOCs select CONFIG_SOC_INTEL_COMMON_BLOCK_LPC,
remove duplicated acpi name assignments.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If418c83caafe5d9e2af135a8946cbe5eb687b9ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Intel CPX-SP FSP ww38 release made some changes to FSP-M header
file. Those changes do not need corresponding soc code change.
TESTED=built image with ww38 FSP RELEASE binary, booted DeltaLake
DVT to target OS.
Change-Id: I320c4a674f9f4d37c30ce6df510f18ad1ae057eb
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add Thread Count in SMBIOS type 4 "Processor Information".
Modify Thread Count 2 according to SMBIOS spec, it should
be the number of threads per processor socket.
TEST="dmidecode -t4" to check.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I0e00ba706eecdc850a2c6a4d876a7732dcc8f755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In case of 64K bootblock the pagetables don't fit, as the CBFS header
also needs a few bytes.
Fixes build error on platforms that use 64KiB bootblock.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I854c5f575e2376827a366cca8d25682c4d90bc8f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37394
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Librem Minis exhibit issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this, so limiting SATA speeds to 3Gbps is no longer needed.
Test: build/boot Librem Mini with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I8b3cbcff7f181bcab35d71e859033578c822bb20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Some Librems have issues with 6Gbps SATA operation on certain
SSDs, setting the Receiver Equalization Boost Magnitude adjustment
resolves this.
Test: build/boot Librem 15v3 with Crucial SATA SSD, observe no issues
booting, no ATA-related errors in dmesg on PureOS 10 / kernel 5.8.7
Change-Id: I078deeff7fc54694393b5b16c41c5d622b332781
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Adds a new port for the Aspire G43T-AM3. It is from an Aspire M3800
desktop model of which I only own the mainboard. The silkscreen label
calls it "G45T/G43T-AM3 V:1.0". In DMI data it is additionally called
Acer EG43M.
The Aspire M5800 model seems to use the same mainboard. The BIOS you can
download from Acer is identical for both.
Various similar mainboards by Acer exist: G41T-AM, G43T-AM, G43T-AM4,
Q45T-AM, to name a few. ECS has some models that are obiously based on
the same design, e.g. G43T-WM and G43T-M.
This model is a microATX-sized board with an LGA 775 socket, four DDR3
DIMM slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based
on the Intel G43 chipset.
The port was started by copying mb/intel/dg43gt (not going to lie here)
and adapting things by looking at dumps from the system when running
with the vendor BIOS. Serial console output is possible by soldering to
a point at the corresponding Super I/O pin.
The service manual for the board was helpful for setting the correct PCI
IRQ links. It can be found publicly on the internet as the "Acer Aspire
M3800 Service Manual".
Working:
- CPUs from Pentium Dual-Core E2160 to Core 2 Quad Q9550 at FSB1333
- Native raminit
- All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
- PS/2 mouse
- PS/2 keyboard (needs CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500)
- USB ports (8 internal, 4 external)
- All six SATA ports
- Intel GbE
- Both PCI ports with various cards (Ethernet, audio, USB, VGA)
- Integrated graphics (libgfxinit)
- HDMI and VGA ports
- boot with PCIe graphics and SeaBIOS
- boot with PCI VGA and SeaBIOS
- Both PCIe ports
- Flashing with flashrom
- Rear audio output
- SeaBIOS 1.14.0 to boot slackware64
- SeaBIOS 1.14.0 to boot Windows 10 (needs VGA BIOS)
- Temperature readings (including PECI)
- Super I/O EC automatic fan control
- S3 suspend/resume
- Poweroff
Not working:
- Resource issues with the VGA BIOS of a PCI rv100-based card
- Super I/O voltage reading conversions
Untested:
- The other audio jacks or the front panel header
- On-board Firewire
- EHCI debug
- VBT (was extracted and added, but don't know how to test)
- Super I/O GPIOs
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add DTT (Dynamic Tuning Technology) support for Tiger Lake based rvp board.
Set power limits and CPU sensor thresholds for DTT based thermal control.
BRANCH=None
BUG=None
TEST=Build and boot on tglrvp board
Change-Id: I0dbee370b8dc9e1e3ae6f1a1101047ac6fd76f53
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
For mainboards using the HP KBC1126 EC interface, but with a different
EC implementation, we don't put the EC firmware in the CBFS image. Add
a Kconfig option to prevent the build system warning on not inserting
the EC firmware.
After this change, building coreboot for EliteBook Folio 9480m will
not have a warning on not inserting the EC firmware.
The build system still builds a working coreboot image for EliteBook
2560p, and gives a warning if not choosing to insert the EC firmware.
Change-Id: I3be83a13d138d3623064ef2803f3e3a340207ead
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With commit f2eb687d19 (soc/intel/{cnl,icl,skl,tgl,common}: Make
changes to send_heci_reset_req_message()) the return value was
changed on a single path. Update the other paths too, even though
it's the discouraged 0-is-failure.
Change-Id: I179a6a4b1e13565dd58c908eb2a9725052a4de9d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
update the telemetry setting for second SDLE testing(for APU power adjusting).
Those values are used to power calibration the APU power and achieving
the best performance.
BUG=b:160698427
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4cf5b8f090befd6a3c4990f44f2f200bc66aa1f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44804
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
