In commit 2609eaaa8f (src/drivers/i2c/rx6110sa: Omit _HID temporarily)
the randomly assigned and therefore wrong ACPI ID for RTC RX6110SA was
removed. In the meantime Seiko-Epson did a great job and registered an
official vendor ID in the ACPI database [1]. Further on, Seiko-Epson
has now assigned the unique Product Identifier for the RX6110SA, which
is '6110'. The assignment of the Product Identifier is controlled by
the vendor and there is no official database where this ID is stored
in. It is up to the vendor to make sure that this ID stays unique.
This patch adds this new vendor and product ID to the driver. Together
with a pending Linux patch this RTC is now useable as ACPI device in
Linux.
[1] https://uefi.org/ACPI_ID_List?search=SECC
Change-Id: I45838162f014a760520692c6dcaae329ad98547d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51176
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Johannes Hahn <johannes-hahn@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This lock bit can be set later, and should also be set for LynxPoint-H.
This eases merging with Broadwell, which already sets this lock bit
after `spi_finalize_ops()` in a dedicated finalisation function.
Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set.
Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks:
IASL build/dsdt.aml
Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20200925
Copyright (c) 2000 - 2020 Intel Corporation
dsdt.asl 222: Name(PSa, Package(){
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_)
dsdt.asl 228: Name(APSa, Package(){
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA)
Execute the command below to fix all occurences:
git grep -l PSa | xargs sed -i 's/PSa/PSA/g'
Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.
Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.
Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the SATA LED blink when coreboot dies. GPIO functions aren't
compiled in for postcar, so add a check to prevent linker failures.
TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and
also blinding LED). Re-install RAM (and re-seat RAM a few times),
boot to OS, and observe SATA LED operating normally, as expected.
Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Backport commit 0cded1f116 (soc/intel/tigerlake: Add SMRR Locking
support) to other client platforms. The SMRR MSRs are core-scoped on
Skylake and Ice Lake, at least. Older platforms do not support SMRR
locking, but now there's seven copies of the same file in the tree. A
follow-up will deduplicate smmrelocate.c files into common CPU code.
I cannot test Jasper Lake nor Elkhart Lake, but they should still work.
As per documentation I do not have access to, Elkhart Lake seems to
support SMRR locking. However, Jasper Lake documentation is unclear.
Tested on Purism Librem Mini v1 (WHL-U i7-8565U), still boots and SMRR
MSRs have the same value on all cores/threads (i7-8565U supports HT).
Change-Id: Icbee0985b04418e83cbf41b81f00934f5a663e30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Booted fine on the first try. Most things work properly, but I haven't
tested them thoroughly. Native raminit chokes with a DIMM in the second
slot, but the first slot works properly.
Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.
Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other
special case) or rev2 (works like CoachZ/Homestar), rev1 used the same
pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still
some people using these, so add in another special case for that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
