b33c6fbfd5
nb/intel/x4x,sandybridge: Move INITRAM timestamps
...
Let's not have CBMEM hooks in between the different
INITRAM timestamps.
Change-Id: I46db196bcdf60361429b8a81772fa66d252ef1a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:36:36 +00:00
4ce0a07f06
nb/intel/x4x,sandybridge: Move romstage_handoff_init() call
...
Change-Id: I6356bb7ea904ca860cbedd46515924505d515791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:35:53 +00:00
b6fc13b3db
nb/intel/haswell: Use cbmem_recovery()
...
For consistency with other nb/intel rename variable from
wake_from_s3 to s3resume.
Change-Id: If94509c4640f34f2783137ae1f94339e6e6cf971
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:35:34 +00:00
74cb3e7869
soc/intel/broadwell: Use cbmem_recovery()
...
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.
Change-Id: I34a123f9fc13bd86264317c7762bf6e9ffd0f842
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:35:21 +00:00
c5c3e3c594
soc/intel/baytrail: Use cbmem_recovery()
...
For consistency with other soc/intel add s3resume variable,
this helps towards unified chipset_power_state.
Change-Id: Ida04d2292aabb5a366f3400d8596ede0dee64839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:35:08 +00:00
6ceec167f5
soc/intel/baytrail: Use a variable for s3resume
...
This helps towards unified chipset_power_state.
Change-Id: I532384ad6c5b2e793ed70f31763f2c8873443816
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-23 02:34:47 +00:00
cdb5b56303
mb/google/oak: Add new DRAM modules K4E6E304EC-EGCG-4GB
...
Samsung K4E6E304EC-EGCG-4GB # 1011
BUG=b:179455694
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass stress test under run-in.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com >
Change-Id: I02cc34157fd03edb7d715a23ed404abc40ef8ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50978
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-23 02:27:35 +00:00
a09559501c
drivers/intel/fsp2_0/memory_init: check if UPD struct has expected size
...
If the UPD size in coreboot sizes mismatches the one from the FSP-M
binary, we're running into trouble. If the expected size is smaller than
the UPD size the FSP provides, call die(), since the target buffer isn't
large enough so only the beginning of the UPD defaults from the FSP will
get copied into the buffer. We ran into the issue in soc/amd/cezanne,
where the UPD struct in coreboot was smaller than the one in the FSP, so
the defaults didn't get completely copied.
TEST=Mandolin still boots.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ia7e9f6f20d0091bbb4abfd42abb40b485da2079d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-02-23 01:32:14 +00:00
ca5ed4879f
mb/google/zork/var/shuboz: Adjust GPIO settings
...
1. GPIO_4 to NC
BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com >
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-23 01:14:58 +00:00
202b1899dc
soc/intel/tigerlake: Enable end of post support in FSP
...
Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.
BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".
Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Signed-off-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 23:20:32 +00:00
3e945f1a23
mb/amd/bilby: updating EC FW specific options for bilby
...
EC does not exist in Bilby platform, so removing EC size from board.fmd
and updating bilby fmap size to 0xfef000.
Removing unused EC FW config options MANDOLIN_HAVE_MCHP_FW and
MANDOLIN_MCHP_FW_FILE.
Change-Id: I9ca4e421b0d80d041ed4046fa20cc16e24a776d0
Signed-off-by: Ritul Guru <ritul.bits@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-02-22 16:00:41 +00:00
c79fc4737d
mb/emulation: Drop cbmem_recovery(0) call in ramstage
...
Calling cbmem_recovery(0) late in ramstage would appear
to remove all CBMEM entries created so far.
Change-Id: I2abb079844c4b41be09354d603ad36e4a56ea2e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50841
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:39:39 +00:00
70243cd801
Revert "lynxpoint: Fix SerialIO ACPI compile issue with recent IASL"
...
This reverts commit 1a25c9cdfdth3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46955
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:37:26 +00:00
3b8ddee47f
configs/config.asrock_b85m_pro4...: Build-test ASan
...
This build-tests ASan support for both romstage and ramstage, because
the Haswell northbridge selects the HAVE_ASAN_IN_ROMSTAGE option. x86
Kconfig selects the HAVE_ASAN_IN_RAMSTAGE option, and Haswell is x86.
Change-Id: I892881d2315c09aa6d9d80903a8399d0f4d648e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Harshit Sharma <harshitsharmajs@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-02-22 07:33:11 +00:00
cf0cd65038
nb/intel/sandybridge: Remove stale FIXME about ECC support
...
Change-Id: Id0c45ff1ee4a2dc4c0f9a82f6a311f7acac156fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-02-22 07:32:37 +00:00
052e439318
mb/google/brya: Fix chip driver and HID for Cr50 TPM
...
ChromeOS does not compile in CONFIG_OF, so PRP0001 will not successfully
register the device with its driver. Change to GOOG0005 to match other
ChromeOS devices with I2C-connected Cr50 TPM.
BUG=b:180657076
TEST=abuild
Change-Id: Ic1d4eb5e12ea7f7e693f1ffd3848e59668ac2deb
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50920
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:32:06 +00:00
cc7acb82c0
tests: Add lib/memchr-test test case
...
Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Change-Id: Idcc824bfd9ca950f377c8f6a5916ffaba450fe73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2021-02-22 07:31:06 +00:00
d75ee46d3c
soc/amd/picasso/acpi: Change PCI0 BAR window
...
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-22 07:29:41 +00:00
0b123dd72e
soc/amd/cezanne/acpi: Add pci0.asl
...
This differs slightly from picasso. The PCI BAR region is between TOM1
and CONFIG_MMCONF_BASE_ADDRESS. This matches what the Intel platforms
are doing. It also matches what linux derives from the e820 tables:
> [mem 0xd0000000-0xf7ffffff] available for PCI devices
Picasso currently declares the region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region.
TEST=Boot majolica and check logs
pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window]
pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window]
pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff]
pci_bus 0000:00: root bus resource [mem 0xd0000000-0xf7ffffff]
pci_bus 0000:00: root bus resource [bus 00-3f]
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I4ff02012795e2166e3a4197071b1136727089318
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50893
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:29:31 +00:00
58a8ad1661
soc/amd: Move root complex SSDT TOM1/TOM2 generation function
...
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.
TOM2 isn't used by any ASL, so we could remove it later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-02-22 07:29:19 +00:00
bde284b585
soc/amd/cezanne/acpi/soc.asl: Add platform.asl
...
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I01adba010bfad1bb4fdf20a8d0ab22aeeebeb10a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-22 07:29:09 +00:00
980721b3ed
soc/amd/cezanne/acpi: Add MMIO devices
...
The devices were copied from picasso with the following modifications:
* UART{2,3} were deleted
* I2C{0,1} were added
* eMMC was removed since it hasn't been validated
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: Iddfb975e9292785d0951dd7bb31c1997d2185abd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-22 07:29:01 +00:00
1156acbb7e
mb/google/guybrush: Enable console UART
...
BUG=b:180530492
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: I468d76d0e061431bc819ec12978203614bfe72b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50919
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Rob Barnes <robbarnes@google.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:28:37 +00:00
86a2324ee0
mb/google/guybrush: Enable guybrush variant
...
Enable the building of guybrush variants and configure the first variant
also called guybrush.
BUG=b:180419462
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: I3bed620378f9152277b4943ead1017f61a21ea82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50845
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:28:26 +00:00
5d47887965
mb/google/guybrush: Enable ACPI tables
...
BUG=b:180419454
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: I1e724e78b5ef378d474063417aa2b7e57a00886f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-02-22 07:28:18 +00:00
40f53f4b87
mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17
...
Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-22 07:26:14 +00:00
cbcae2744a
mb/google/dedede/var/drawcia: Configure IRQ as level triggered for elan_ts
...
Follow elan's suggestion to configure IRQ as level trigger.
BUG=b:180570924
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: I292670580b4c2c18ed0c20a9fbb4ad4289f4eca6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-22 07:25:50 +00:00
a3868296ce
nb/intel/ironlake: Do not call collect_system_info twice
...
Move wait for TXT and early ME init out of `collect_system_info`, and
then drop the first call to it. Also drop a useless register read.
Tested on out-of-tree HP 630, still boots.
Change-Id: I9b167f44cbd96864bf1e8b616576af19cbbfd90c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49581
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:25:37 +00:00
e9fa37894e
soc/intel/xeon_sp: Define all SMI_STS bits
...
As per document 336067-007US (C620 PCH datasheet), add macros for all
bits in the SMI_STS register. These will be used in common code.
Change-Id: I1cf4b37e2660f55a7bb7a7de977975d85dbb1ffa
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50915
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 07:25:09 +00:00
12e2e0e609
arch/arm/armv7/thread.c: Remove stale file
...
This file is never built. Plus, `CONFIG_STACK_BOTTOM` does not exist.
Change-Id: I111b20e3443dca701ee8666d44261a00a161d83f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2021-02-22 07:24:26 +00:00
5276c34654
mb/amd/padmelon: Drop unnecessary PADMELON_SOC_IN_USE option
...
The SoC can be selected in the corresponding option choices directly.
Change-Id: I226c500dd7370f4610b0117a9e70d727f1d66951
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-22 07:24:12 +00:00
3d695d2e6a
mb/google/oak: Clean up TPM Kconfig
...
Rowan was the only Oak variant that used TPM2. However, it was removed
in commit 0aa1f9e905th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2021-02-22 07:23:58 +00:00
2a58e187af
mb/intel/harcuvar: Drop build guards for ENABLE_FSP_MEMORY_DOWN
...
Ensure the code gets build-tested for CONFIG_ENABLE_FSP_MEMORY_DOWN=n.
Change-Id: I6213e3e0ea3b2acfc97017739ac069ee3811d742
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-02-22 07:23:36 +00:00
77330e5b15
mb/amd/padmelon: Replace HAVE_S3_SUPPORT symbol
...
Replace it with `HAVE_ACPI_RESUME`, which defaults to n for this board.
Change-Id: Ibb07c0d001ded8d7ff991bf63607872bf4b79c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-02-22 07:23:16 +00:00
15cbc3b599
soc/intel/tigerlake: Add CrashLog implementation for intel TGL
...
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com >
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-02-22 07:22:50 +00:00
619c60f94c
soc/rockchip/rk3399/sdram: Remove superfluous parameter
...
Remove extra parameter in phy_dll_bypass_set, since it does not
depend on the channel at hand.
Signed-off-by: Moritz Fischer <moritzf@google.com >
Change-Id: Iae09a6053daf58bf12604e1903c754dc9f1e986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: ron minnich <rminnich@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2021-02-22 07:21:48 +00:00
63b87e985c
Document Gigabyte GA-G41M-ES2L
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To replace wiki page https://www.coreboot.org/Board:gigabyte/ga-g41m-es2l
+ configs/config.gigabyte_ga-g41m-es2l
+ lshw output examples
+ memory modules compatibility
Tested in Devuan 4 Chimaera.
Tested from exact steps from this documentation.
Change-Id: Ib45cfea15b43d7399e9d209f7ba7c6b24fe860dd
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Evgeny Zinoviev <me@ch1p.io >
2021-02-22 07:21:30 +00:00
f595984043
Documentation: move coding_style.md inside contributing/
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Keep less files in the root directory.
Change-Id: I9eebd0b0826181340ead41af5284362d1cca09d7
Signed-off-by: Alexey Vazhnov <vazhnov@boot-keys.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
2021-02-22 07:20:59 +00:00
3dba88401d
mb/google/zork/var/vilboz: adjust USB phy settings for all USB ports
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Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 05:58:24 +00:00
738aaa24d3
mb/intel/shadowmountain: Add the romstage code
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This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com >
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-22 05:46:58 +00:00
43f6598b27
mb/: Drop the provided name in chip_ops
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Little point to replicate a string already provided both
as a global Kconfig and global mainboard_part_number.
Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: ron minnich <rminnich@gmail.com >
2021-02-21 22:54:05 +00:00
bb6bf5a1d8
mb/lippert/frontrunner-af: Split sections from dsdt.asl
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Added file acpi/sleep.asl is really a copy from persimmon with debug
statement and some comments removed.
Added file acpi/gpe.asl is slightly modified copy from persimmon with
changes that seem valid, considering the other changes present in ASL
for the board.
Rename existing usb.asl to usb_oc.asl for consistency.
Change-Id: I493ad1c110380378bad80e49cd888f47fbe41a92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:41:06 +00:00
1943b27ea3
AGESA fam14 boards: Drop _SI scope with _SST in ASL
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Change-Id: Ieb2f7a6b2721ddeef6945c3e0a0f4cc5627dd533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:40:06 +00:00
49bc3b7aee
AGESA,binaryPI boards: Drop _SI scope with _SST in ASL
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Change-Id: I0fca35753c93ba928a0f67bb68a6cfdc26c0e756
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:39:24 +00:00
c0733e1639
ACPI: Use common OperationRegion for PCI_MMCONF
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Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-20 21:38:54 +00:00
c92efa3363
AGESA,binaryPI boards: Move common PCBA in ASL
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Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:38:11 +00:00
c308f021d2
AGESA,binaryPI boards: Drop unused variables in ASL
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Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:37:42 +00:00
c8d7c4834a
AGESA fam14 boards: Move include for usb_oc.asl
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Do this for consistency with later platforms.
Change-Id: Ia4903b40a8f617c59868aaa116115fa23603438c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:37:24 +00:00
ff9ba54ce1
sb,soc/amd: Drop OSFL method in ASL
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Variable OSVR had a static value of 3 and OSFL() did not
actually call _OSI or _OS methods.
The conditional in HDA _INI method of OSVR is dropped and
use of DMA NoSnoop attribute remains disabled to retain
previous behaviour. For soc/amd/picasso a different decision
was made in CB:40782 as HDA _INI method was just dropped and
default configuration enables use of DMA NoSnoop attribute.
Change-Id: I967b7b2afbb43253cccb4b77f6c44db45e2989e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50592
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-02-20 21:37:11 +00:00
b484609a02
sb/amd/cimx/sb800: Drop OSFL method in ASL
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Method only set variable OSRV, which nobody evaluates.
Change-Id: Ia21b544eaaa61a8fc634eb568b4c7401a225eb76
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-02-20 21:33:39 +00:00
