Command timing is the absolute value of the most negative `pi_coding`
value across all ranks, or zero if there are no negative values. Use the
MAX() macro to ease proving that `cmd_delay` can never be negative, and
then drop the always-false underflow check.
The variable type for `cmd_delay` still needs to be signed because of
the comparisons with `pi_coding`, which is a signed value. Using an
unsigned type would result in undefined and also undesired behavior.
Change-Id: I714d3cf57d0f62376a1107af63bcd761f952bc3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Clock is a differential signal and propagates faster than command and
control, therefore its timing needs to be offset with `pi_code_offset`.
It is also a periodic signal, so it can safely wrap around.
To avoid potential undefined behavior, make `clk_delay` signed. It makes
no difference with valid values, because the initial value can be proven
to never be negative and `pi_code_offset` is always positive. With this
change, it is possible to add an underflow check, for additional sanity.
Change-Id: I375adf84142079f341b060fba5e79ce4dcb002be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 7584e550cc (nb/intel/sandybridge: Clean up program_timings)
introduced this condition along with a comment that says the opposite.
Command and clock timings always need to be computed, so drop both the
nonsensical condition and the equally-worthless corresponding comment.
Change-Id: I509f0f6304bfb3e033c0c3ecd1dd5c9645e004b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
To allow other platforms to reuse this code, extract it into a separate
compilation unit. Since HPET is enabled through the southbridge, place
the code in the southbridge scope. Finally, select the newly-added
Kconfig option from i82801gx and replace lpc.c `enable_hpet` function.
Change-Id: I7a28cc4d12c6d79cd8ec45dfc8100f15e6eac303
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Wrap `r` in parentheses to avoid unexpected behavior with compound
expressions. This prevents `CxDRBy_BOUND_MB(r+1, base)` from triggering
undefined behavior when `r = 2`, as the shift would be greater than 32.
Change-Id: I14235b2708ab502d842da677451c14203a469b45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49261
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow adjusting the phase shift of the various I/O signals, the
memory controller contains several PIs (Phase Interpolators). These
devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`,
and the desired phase shift is specified in a register. For shifts
larger than one QCLK, there are `logic delay` registers, which allow
shifting a whole number of QCLKs in addition to the PI phase shift.
The number of PI ticks in a QCLK is often used in raminit calculations.
Define the `QCLK_PI` macro and use it in place of magic numbers. In
addition, add macros for other commonly-used values that use `QCLK_PI`
to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.
Formula for conversion of power cycle delay:
gpu_panel_power_cycle_delay_ms =
(gpu_panel_power_cycle_delay - 1) * 100
Formula for all others:
gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10
The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.
Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.
Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.
Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.
Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.
Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Native raminit only supports 1.5V operation, but there are DIMMs which
request 1.65V operation in XMP profiles. Add an option to force XMP to
be used when the requested voltage isn't supported, which will run the
DIMMs at 1.5V with XMP timings. Consider this to be overclocking.
Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Pointers to structs can be very useful, especially when they point to an
array element. In this case, changing one pointer allows the function to
be rewritten more concisely, since most redundancy can be eliminated.
Tested on Asus P8Z77-V LX2, still boots. No functional difference.
Change-Id: I7f0c37ea49db640f197162f371165a6f8e9c1b9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most ofte, `iosav_run_once` precedes a `wait_for_iosav` call. Add a
helper function to reduce clutter. The cases where `iosav_run_once`
isn't followed by `wait_for_iosav` will be handled in a follow-up.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic76f53c2db41512287f41b696a0c4df42a5e0f12
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the purpose of each training algorithm is clear, replace the
last instances of the original names in comments and print statements
with the current, correct names. Also, print which channel has failed
command training, for completeness and consistency with other errors.
Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use absolute values for the Rx and Tx bus timings instead of values
relative to the CA (Command/Address) bus timing. This makes the
calculations more accurate, less complex and less error-prone.
Tested on Asus P8H61-M PRO, still boots. Training results do not seem to
be affected by this patch, and the margins roughly have the same shape.
Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple indepent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or
fb_new_framebuffer_info_from_edid.
Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Do not combine the host bridge device ID with the CPU stepping because
it is confusing. Although Sandy/Ivy Bridge processors incorporate both
CPU and northbridge components into the same die, it is best to treat
them separately. Plus, this change enables moving CPU stepping macros
from northbridge code into the CPU scope, which is done in a follow-up.
Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 7f1363d9b4 (nb/intel/sandybridge: Program MR2 shadow register)
has a bug where the system locks up and power cycles when booting Linux,
but is still able to pass memtest86+ with flying colors. The issue will
occur when the following conditions are true:
- CPU is Ivy Bridge
- Memory speed is not greater than 1066 MHz (DDR3-2133 or slower)
- System contains dual-rank DIMMs
- The second rank of the dual-rank DIMMs is mirrored
- All DIMMs support Extended Temperature Range
- At least one of the DIMMs does not support Auto Self-Refresh
If all of these conditions are met, the final value of the MR2 Shadow
registers configures the memory controller to issue a MRS command to
update MR2 before entering self-refresh mode, but indicates that rank
mirroring is not required (the first rank on a DIMM is never mirrored).
Before the memory controller enters self-refresh, it sends MRS commands
to all ranks to update MR2, but the missing address and bank mirroring
means DRAM chips on mirrored ranks instead clobber MR1 with junk data.
With garbage in MR1, the mirrored ranks no longer function properly,
which ultimately leads to all hell breaking loose (undefined behavior).
The condition is backwards, since only odd ranks can be mirrored. To
avoid this problem completely, simply remove the condition. The final
register value will still be correct, since the bits are always ORed.
Tested on Asus P8Z77-V LX2, fixes booting Linux with dual-rank DIMMs.
Change-Id: Iceff741eb85fab0ae846e50af0080e5ff405404c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There's no need to wrap these macros with casts. Removing them allows
dropping more casts in `early_init.c`.
To avoid binary changes the casts are put into the
{MCH,DMI,EP}BAR{8,16,32} macros instead where they are needed to reach
the right memory locations.
Change-Id: Icff7919f7321a08338db2f0a765ebd605fd00ae2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces two new CBFS API functions which are equivalent to
cbfs_map() and cbfs_load(), respectively, with the difference that they
always operate on the read-only CBFS region ("COREBOOT" FMAP section).
Use it to replace some of the simple cases that needed to use
cbfs_locate_file_in_region().
Change-Id: I9c55b022b6502a333a9805ab0e4891dd7b97ef7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39306
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
