<stdio.h> header is used for input/output operations (such as printf,
scanf, fopen, etc.). Although some input/output functions can manipulate
strings, they do not need to directly include <string.h> because they
are declared independently.
Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards are not commerically available so can be removed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Icc853a9df44a4a770db76e119644f0b4c7fcc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
CPUID is the same for Alder Lake and Raptor Lake S and HX variants.
To reduce the confusion and concerns how to name the macros, remove
the suffixes from macros and platform reporting strings. Thankfully
the stepping names are unique across mobile (P suffixed) and desktop
(S and HX suffixed) SKUs. Distinguishing the S from HX is possible via
host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Board id is same so use cpuid to decide to use ADL or RPL VBT.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board
Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
When booting ADL RVP, coreboot is unable to load VBT binary as
makefile will rename VBT binary to "vbt.bin" when building
coreboot.rom.
The reason for having this function is that chromeOS has emerge
tool to streamline the VBT stitching process to support multiple
VBTs for different RVP boards; while we only need 1 vbt for generic
non-chromeOS usage. Hence add a chomeos kconfig to guard this.
TEST=Able to boot ADL RVP DDR5 with DP display.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.
VBT files added at chrome-internal:4138272
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This will enable to include multiple VBT binaries in a single image
and load corresponding file according to HW configuration.
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to pick the right vbt from cbfs according to
SKU-ID.
Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
List of changes:
1. Add devicetree.cb config parameters related to FSP-S UPD
2. Configure GPIO as per ADL-P RVP
3. Add files required for ramstage(ec.c, mainboard.c)
4. Add smihandler.c for SMM
5. Add devicetree changes as below
- USB OC PIN programing
- GPE configuration
- SATA port mapping
- LPSS configuration
- Audio configuration
- IA common SoC configuration
- EDP configuration
- TCSS USB configuration
- Enable S0ix
TEST=Able to boot ADL-P RVP without Chrome EC (using on-board EC) with
UART log over legacy UART0 port as 0x3f8 with NVME at RP9 reach till
depthcharge payload.
Change-Id: I120885956c88babfa09d24ce1079d49306919b8a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
