Commit Graph

39153 Commits

Author SHA1 Message Date
Arthur Heymans
f879d36551 device/pci_device.c: Improve pci_bridge_route() readability
Both the secondary and subordinate bus numbers are configured in this
function but it's not easy to search for in the tree as the PCI writes
are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate
variables and PCI config writes to improve the readability.

Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-02 13:15:12 +00:00
Rex-BC Chen
c89f252608 soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz test
The XTAL 26MHz test failed on krabby, so we adjust RTC capid from
default value 0x88 to 0xC0 for MT8186. We also add a new log message
to show the capid value which is read from MT6366.

This implementation is according to chapter 5.13 in MT8186 Functional
Specification.

BUG=b:218439447
TEST=set capid to 0xc0.
TEST=XTAL 26MHz test passed.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:24 +00:00
Rex-BC Chen
025fb17372 soc/mediatek: remove unused RTC_GPIO_USER_MASK
RTC_GPIO_USER_MASK is not used in any drivers, so we remove them.

BUG=none
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-02 13:13:10 +00:00
Zhuohao Lee
d036a70d74 mb/google/brya: enable the SPD_CACHE_ENABLE
google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.

Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:47 +00:00
Zhuohao Lee
84eb532ec3 mb/google/brya/variants: add the smbus addr for dimm1
Align the setting with the adlrvp

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask

Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:10:33 +00:00
Zhuohao Lee
b8b40964fc mb, soc: Add the SPD_CACHE_ENABLE
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.

BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
     the device could speed up around 150ms with this feature.

Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:10:21 +00:00
Gaggery Tsai
9d0fc3f396 mb/google/brya/var/vell: Remove Rcomp settings
This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.

BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
     PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
     filled properly by MRC.

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-02 13:09:28 +00:00
Casper Chang
7a7a533725 mb/google/brya/var/primus{4es}: modify GPP_B3 as unlocked
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.

BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
     test reboot 30 cycles passed on primus.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2022-03-02 07:41:43 +00:00
Julian Schroeder
017ad9a41d soc/amd/common/fsp/fsp_validate.c: print warning instead of error
If an AMD FSP binary has no valid image revision information, print a
warning instead of an error.

Change-Id: Ie9c5a387b81205fe93382778090260e41e261776
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62349
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-01 20:59:29 +00:00
Raul E Rangel
554f9e6b20 mb/amd/chausie: Always enable developer mode
Chausie doesn't have recovery mode buttons so it's impossible to
manually enter recovery mode to enable developer mode. This means we
need to force developer mode.

BUG=none
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 17:29:58 +00:00
Tim Wawrzynczak
63632d7d82 security/tpm: Add vendor-specific tis functions to read/write TPM regs
In order to abstract bus-specific logic from TPM logic, the prototype
for two vendor-specific tis functions are added in this
patch. tis_vendor_read() can be used to read directly from TPM
registers, and tis_vendor_write() can be used to write directly to TPM
registers.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I939cf5b6620b6f5f6d454c53fcaf37c153702acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-01 16:52:31 +00:00
Tim Wawrzynczak
591c7ebf18 drivers/tpm/spi: Convert static functions to enum cb_err return types
Instead of using raw integers to indicate success/failure, enum cb_err
can be used to makes things clearer, so this patch converts most
functions to return that instead of int.

TEST=boot to OS on google/dratini, no TPM errors seen

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifb749c931fe008b16d42fcf157af820ec8fbf5ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-01 16:52:21 +00:00
Kevin Chiu
d736fd4ea7 mb/google/guybrush/var/nipperkin: update thermal setting
Enable STT and decrease sustained_power_limit_mW to 12W

BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
     update the thermal setting value by measurement and
     pass the thermal performance test

Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-01 11:57:58 +00:00
MAULIK V VAGHELA
a4af1b58a5 intelblocks/cse: Skip sending EOP during S3 resume
coreboot should skip sending EOP during S3 resume since CSE doesn't
require EOP in resume path.

Currently EOP is being sent during PAYLOAD_BOOT or PAYLOAD_LOAD stage
which doesn't get called during S3 resume.

In case EOP is moved in earlier stage, coreboot might send EOP in S3
resume as well. This patch adds check before calling cse_send_eop.

BUG=b:211085685
BRANCH=None
TEST=Check by moving EOP to earlier stage. EOP sending is skipped during
S3 resume.

Change-Id: I8f22446974bc1e7b2d57468633c36bb99ffe1436
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-03-01 11:57:38 +00:00
Sean Rhodes
5da05b6e35 mb/starlabs/lite: Add StarLite Mk III
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iddbf2022d03735d6a0e6d098c21643f5fdc875f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-01 11:56:26 +00:00
Sean Rhodes
c64626c9d9 ec/starlabs/merlin: Remove unused keyboard.asl
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife0f5b8b6102b543a7ace6739fa44d32ca80dcde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:55:06 +00:00
Sean Rhodes
f6ea89d684 ec/starlabs/merlin: Add spaces to adhere to coding style
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0e965513d5888398834cab8c8445e97372f2b115
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-01 11:54:53 +00:00
Krishna Prasad Bhat
e1ff978c9a mb/intel/adlrvp: Enable eMMC device for ADL-N RVP
Add eMMC related GPIO pins in gpio_n.c and enable eMMC device for Alder
Lake N RVP from devicetree.

Change-Id: I66e015aa921383cfc21cfe261377ae6b3b58cbab
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-03-01 11:54:26 +00:00
Raul E Rangel
56dbb4ac39 lib/Makefile: Add ability to specify -ldflags for rmodules
This will allow linker flag customization for rmodules.

BUG=b:221231786
TEST=Build guybrush with patch train and verify ldflags are passed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib65476759e79c49d90856dcd7ee76d7d6e8a679a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-28 22:02:22 +00:00
Fred Reitberger
527d73f1bf mb/amd/chausie/Kconfig: Add EC FW to RO_REGION_ONLY
Include chausie EC and EFS only in the RO region when building with
vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B
regions.

Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 21:28:13 +00:00
Tim Wawrzynczak
7a94ad720e soc/intel/common/block/acpi: Return existing Object for _DSM subfunction
Currently the LPIT Get Constraints _DSM subfunction returns a package
containing the path to a nonexistent device (\NULL). This is used to
work around an issue with Windows, where returning an empty package will
cause a BSOD.  However, using this non-existent device can also cause
confusion, as on Linux, it shows an error in dmesg, e.g.

    ACPI Error: AE_NOT_FOUND, While resolving a named reference package
    element - \NULL (20200925/dspkginit-438)

Therefore, this patch modifies this returned package slightly to include
the path to ACPI_CPU_STRING for CPU 0, which should always be emitted on
Intel platforms that use the PEP driver.

Tested on google/brya0 on ChromeOS 5.10 kernel
Tested with current Windows 11 ISO

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If74a1620ff0de33bcdba06e1225c5e28c64253e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.corp-partner.google.com>
2022-02-28 18:50:13 +00:00
Arthur Heymans
b4ba289fa5 cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
This will allow to migrate all platform to the parallel_mp init code
and drop the old lapic_init code.

Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58700
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:33:59 +00:00
David Wu
6179f7b618 mb/google/brya/var/kano: add enable_off_delay_ms to 30
Kano changes load switch of touch screen to TPS22914C (is not with
discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms
to fix DUT can't enter S0ix issue.

BUG=b:220811619
TEST=Boot kano to OS and run S0iX test 2500 cycles.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2022-02-28 13:32:04 +00:00
Jon Murphy
e6e46c968a mb/google/skyrim: Enable PCIe devices in devicetree
BUG=b:214414301
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:31:40 +00:00
Jon Murphy
0bc013b15a mb/google/skyrim: Enable AP <-> D2 communication
Configure D2 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for D2 device and enable the required
config items.

BUG=b:214414776
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:31:27 +00:00
Jon Murphy
ee67ddc707 mb/google/skyrim: Add eSPI configuration
BUG=b:214413613
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:58 +00:00
Jon Murphy
4f4f32ba20 mb/google/skyrim: Add initial fch irq routing
BUG=b:214417045
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:30:31 +00:00
Jon Murphy
410b7cb97e mb/google/skyrim: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.

BUG=b:214414677
TEST=Build

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:30:13 +00:00
Jon Murphy
f79cc51b3f mb/google/skyrim: Log mainboard events to elog
BUG=b:214414851
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:57 +00:00
Jon Murphy
6ad5f4ec16 mb/google/skyrim: Add ACPI configuration for USB ports
The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-28 13:29:42 +00:00
Jon Murphy
6e368f79ec soc/amd/sabrina: Add XHCI configuration
Add xhci 2 controller support for additional USB port/ Dummy setting

BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5c8885bf46ddbfc85b31585a4da7f746c1a6bcd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-28 13:29:24 +00:00
Cliff Huang
96bb0ba9e7 drivers/wwan/fm: Add support for _PTS for Fibocom 5G WWAN
Add DPTS (device prepare to sleep) method that is to be called in
mainboard's \_SB.MPTS, which is called in _PTS.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie308f74940a33711a398bc11d0550cb06b55cdcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-28 13:29:02 +00:00
Nico Huber
f514b8ae82 device/pci_device: Fix PCIe bridge detection
PCI bus 0 is not below any PCI device. In case of pci_domain_scan_bus(),
it's our virtual `domain` device.

Expecting a PCI device above bus 0 resulted in undefined behavior for
all boards with PCI. Only boards with a PCI device 00:00.0 that looked
like a PCIe bridge showed issues, though (e.g. OCP/DeltaLake).

Change-Id: I1fd68b9dc0d2e388ec2bbba4adbadd33e14f0171
Signed-off-by: Nico Huber <nico.h@gmx.de>
Fixes: commit 777ffff442 (device/pci_device.c: Scan only one device for PCIe)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62376
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-28 13:28:12 +00:00
David Wu
e6ab52e289 mb/google/brya/var/kano: Add wifi sar table
1. Add wifi sar table for kano
2. Set EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG

BUG=b:214393458
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Icddd583e5ee31e08b615df6fb2f4ceeb7f0c8131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2022-02-28 13:27:53 +00:00
Angel Pons
0cd1a87d50 sb/intel/lynxpoint: Fix up comment
Change-Id: Ie46b63d192b8e4871442f6b0db5b1575168f89ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2022-02-28 13:27:22 +00:00
Frank Chu
9fc741d32f mb/google/dedede/var/pirika: Add Wifi SAR for pasara
Add wifi sar for pasara

BUG=b:216411442
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ida475307c8448c5c2758c289da7708484bcb89e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-28 13:27:11 +00:00
Jon Murphy
b4156412db mb/google/skyrim: Enable USB controllers in devicetree
BUG=b:214413631
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:39:02 +00:00
Jon Murphy
10ff9375ae mb/google/skyrim: Enable internal graphics
BUG=b:214416935
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-26 00:19:36 +00:00
Jon Murphy
4b2e04a53b mb/google/skyrim: Enable console UART
BUG=b:214414501
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:18:40 +00:00
Jon Murphy
eab1827b66 mb/google/skyrim: Set up FW_CONFIG
BUG=b:214415048
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:18:09 +00:00
Jon Murphy
e3e1801a33 mb/google/skyrim: Enable eSPI SCI events
Enable ESPI SCI events

BUG=b:214416630
TEST=builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:40 +00:00
Jon Murphy
2a7445a165 mb/google/skyrim: Add smihandler
BUG=b:214415408
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:25 +00:00
Jon Murphy
cbf0f98c61 mb/google/skyrim: Enable Chrome EC
BUG=b:214413613
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:17:10 +00:00
Jon Murphy
9e00571b49 mb/google/skyrim: Enable variants for Skyrim
BUG=b:214414033
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:16:39 +00:00
Jon Murphy
af025d6ee1 mb/google/skyrim: CONFIG_CHROMEOS
BUG=b:214415401
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:16:17 +00:00
Jon Murphy
960fb2f4b8 mb/google/skyrim: Enable ACPI tables
Add GPIO initialization and ACPI generation for tables

BUG=b:214415303
TEST=builds
BRANCH=none

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 00:15:58 +00:00
Subrata Banik
4de2c342fb soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
This fixes no practical problem, especially for coreboot where only
one process should access the SPI controller. It makes the code look
more spec compliant.

As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.

Software must initiate the next SPI transaction when this bit is 0.

Add non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.

BUG=b:215255210
TEST=Able to boot brya and verified SPI read/write is successful.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2022-02-26 00:15:28 +00:00
Raul E Rangel
737ad67d12 soc/amd/common/psp_verstage: Add missing post codes on S0i3 resume
We print these out in the normal flow, so lets add them for S0i3 resume
as well.

BUG=b:221231786
TEST=Perform suspend/resume cycle on guybrush and verify we get the new
POST codes.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia7d607453d58084868cfa50770fd0f370b2ea2bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-02-26 00:09:27 +00:00
Raul E Rangel
5e0ed5016c soc/amd/{common/psp_verstage,soc/picasso}: Remove workbuf shrinking
This feature was never used. Let's remove it to keep things simple.

BUG=221231786
TEST=Boot test guybrush and morphius and verify transfer buffer is
correctly passed.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I93a284db919f82763dcd31cec76af4b773eb3f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-02-26 00:09:18 +00:00
Zhuohao Lee
0b108a14c0 mb/google/brask: Update PCH power cycle related durations
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.

BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.

Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-25 20:46:19 +00:00