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23 Commits

Author SHA1 Message Date
Michael Niewöhner
a911216926 docs: intel fsp: add memory retraining bug on SPS systems 
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.

Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-11-19 12:56:10 +00:00
Marshall Dawson
86278a0361 Documentation: Add amd_blobs license agreement text 
AMD has generated a simpler and more flexible license agreement for
using proprietary precompiled binary images.  The new agreement is
intended to cover all blobs in the directory structure below where
the license resides and eliminates any unique agreements previously
provided for individual products.

Add a description of the repo, as well as the license agreement it
contains.

Change-Id: Ia3dbc1a5259a2512281ea87b7e55fb3134b3b3c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-10-30 21:42:40 +00:00
T Michael Turney
7783c606a4 sc7180: Provide initial SoC support 
Change-Id: Iddcef560c1987486436b73ca1d5fc83cee2f713c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2019-10-21 09:06:55 +00:00
Andrey Petrov
ee0b7ad683 mainboard/ocp/monolake: Hide IIO root ports before memory init 
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.

TEST=the patch was ran on affected HW and success was reported

Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-10-16 14:11:17 +00:00
Richard Spiegel
6453c9062b Documentation/soc/amd: Add Family 15h 
Create documentation for AMD Family 15h.

BUG=none.
TEST=none.

Change-Id: Iaab4edc431329a691283121494595f3797c566c6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2019-10-01 15:13:29 +00:00
Subrata Banik
fb6ea0af40 Documentation/soc/intel/fsp: Add link for external FSP2.1 spec 
Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35238
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-04 10:56:22 +00:00
Patrick Rudolph
96d8e43178 Documentation: Add FSP bugs 
As Intel doesn't even document known bugs add a list of
FSP bugs here.

Change-Id: I07819b83fb0c9437fc237472dfe943f78738347a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34239
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-07-15 07:14:57 +00:00
Arthur Heymans
b3af349284 soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INIT 
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.

Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.

Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-07-10 10:14:39 +00:00
Felix Singer
9b7e990d18 doc/mb/upsquared: Add documentation 
This patch adds documentation about the UP² mainboard
and the IFWI used by Apollolake platform.

Change-Id: Ic708ddbd2616eee4e5ec2740b3eac18b408bde38
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-06-17 14:26:42 +00:00
Marshall Dawson
a2455b2967 Documentation/soc/amd: Add Family 17h 
Begin a directory for AMD soc devices and add an explanation of
how Family 17h works.  Newer AMD systems use a unique paradign
for initializing the x86 processors.

Change-Id: I7bd8649996add80747f6a60b9dfd35a94a560be1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2019-06-13 18:03:28 +00:00
Patrick Rudolph
345d202d66 Documentation: Add FIT 
Describe the Firmware Interface Table and reference useful documentation.

Change-Id: I00abc1fd13be7b48d56ba8cb65d2542ed07f9017
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2019-04-30 08:18:57 +00:00
Subrata Banik
413f5208f0 Documentation/soc/intel: Add MP Initialization document 
This patch provides documentation for MP initialization
option available in coreboot.

Change-Id: I055808e2ddf03663e1ec5d3d423054d1caa911cb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-03-26 11:21:23 +00:00
Subrata Banik
b0f4456aed Documentation/soc/intel/fsp: Move mp_service_ppi document in corrct directory 
This patch moves mp service ppi document from icelake/MultiProcesorInit.md
to ppi/mp_service_ppi.c.

Change-Id: I1bbaeb2644f219b5a1fda0c7c4b594184d53958c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31840
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-03-19 21:41:34 +00:00
Subrata Banik
ebac8c772f Documentation/soc/intel/fsp/ppi: Document new feature to dispatch external PPI 
Some new feature added into FSP specification to perform dispatching
of external PPI service from boot firmware (coreboot) to FSP.

Change-Id: Iaf6b54ccd27e21860539bb2a9966054fdb027108
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31839
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-03-12 04:23:58 +00:00
Subrata Banik
abc5130108 Documentation/soc/intel: Add documentation for Intel FSP 
This patch combines open source documentation for Intel FSP
specification.

Change-Id: I3a8bc0198a1e01ec019139b728834713978501ba
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31838
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-03-12 04:23:00 +00:00
Jonathan Neuschäfer
dca74c16a3 Documentation/soc/intel/icelake: Fix references between documents 
Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-19 05:17:58 +00:00
Jonathan Neuschäfer
84eb41d74c Documentation/soc/intel/icelake: Fix indentation in numbered list 
Without this patch, the numbers restart at 1 at several points in the
HTML output.

Change-Id: Ie3634775ed9f993b1181785c58d72834183336e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/c/30156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
 2018-12-19 05:17:39 +00:00
Subrata Banik
92d7017a04 Documentation/../../icelake: Add Ice Lake coreboot development documentation 
Add documentation for Ice Lake processor family coreboot development.

Documented so far:
* What is Ice Lake
* Development Strategy
* Create coreboot Image
* Flashing coreboot

Change-Id: Ief4df6ca11f95b75ecddeb560f7887bfadced086
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2018-11-27 08:56:05 +00:00
Patrick Rudolph
7187758038 Documentation: Fix markdown highlighting 
Fix some code blocks that use invalid Markdown syntax.

Change-Id: I8cfe63b2c21ae93923f88bbf7ef4cfb8dccdb5ef
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/29207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 2018-10-22 12:02:15 +00:00
Tom Hiller
9990943782 Documentation: Add code_development_model.md to soc/intel/index.md 
Fixes Sphinx WARNING document isn't included in any toctree

Change-Id: I956ed23d87c7cbd65383cc64a6af7161e90d6611
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/27593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2018-07-24 09:12:37 +00:00
Maulik V Vaghela
a6b3b4dd8f Documentation/soc/intel: Add common code design document 
Add common code design document support Intel SoCs such as Skylake,
Cannonlake and Apollolake onwards.

Documented items:
*Introduction
*Design Principle
*Common code development and status
*Common code structure
*Benifits

Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 2018-06-30 03:39:07 +00:00
Patrick Rudolph
8c986ab263 Documentation: Add cavium SoC and mainboard 
* Add documentation for CN81XX SoC
* Add documentation for CN81XX EVB SFF mainboard
* Add documentation for BDK
* Add documentation for BOOTROM and BOOTBLOCK behaviour
* Alphabetically sort vendors

Change-Id: Ibfcd42788e31f684baed658dc3c4dfe1b8e4f354
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
 2018-06-19 18:09:04 +00:00
Philipp Deppenwiese
438b463a8f Documentation: Update index.md and move files 
* Add more subdirectories and index.mds.
* Move "getting started" and "lessons" into sub-directories.
* Move "NativeRaminit" into northbridge/intel/sandybridge folder.
* Move "MultiProcessorInit" into soc/intel/icelake folder.
* Reference new files

Change-Id: I78c3ec0e8bcc342686277ae141a88d0486680978
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2018-05-30 09:14:48 +00:00