If available, use data from MEMINFO CBMEM table and saved handles
from type 17/19 tables to generate type 20 (Memory Device Mapped
Address) SMBIOS table.
Windows 10/11 and some other OSes use this table to report the total
memory available on a given device.
Change-Id: I2574d6209d973a8e7f112eb3ef61f5d26986e47b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
variant_has_pcie_wwan helper returns true if gpp_bridge_2 PCIe engine is
enabled. On some variants, this engine is used by storage controllers.
Fix it by adding a weak override that returns no PCIe WWAN by default.
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that PCIe WWAN is
enumerated on boards where it is stuffed.
Change-Id: I07b9dd8fc5c8c3e1557f9268c1176d4a3cade1af
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
S3 is not currently functional on Guybrush. Remove support from ACPI.
BUG=b:202401767 b:181766974
TEST=Boot Guybrush
Confirm 'deep' is not in /sys/power/mem_sleep
Confirm S0ix suspend/resume still works
BRANCH=None
Change-Id: I9ed3e051f7f2e411670649ac2528a6f40229bdc6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Files used by this test are in: tests/data/lib/lzma-test/
file.bin - files with uncompressed data
file.lzma.bin - files with LZMA-compressed data from file.bin
How to prepare compressed file:
util/cbfs-compression-tool compress file.bin /tmp/file.lzma.bin lzma
dd if=/tmp/file.lzma.bin of=file.lzma.bin skip=8 ibs=1
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Id75e0b41991382d4c391b031862106de58eacdf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
`cse_fw_update()` is currently checking whether an update is required
by comparing versions once and then again comparing versions later in
`cse_is_downgrade_instance()` to determine if the update is an upgrade
or downgrade. Additionally, if CSE RW partition is corrupt (determined
based on `cse_is_rw_bp_sign_valid()`), `cse_is_downgrade_instance()`
ends up using the corrupted version information to determine if it is
a downgrade instance.
This change reorganizes the firmware update checks to return different
status values:
1. CSE_UPDATE_NOT_REQUIRED: No update required. Versions match.
2. CSE_UPDATE_UPGRADE: Update required and it is an upgrade.
3. CSE_UPDATE_DOWNGRADE: Update required and it is a
downgrade (requires data clear).
4. CSE_UPDATE_CORRUPTED: `cse_is_rw_bp_sign_valid()` failed and hence
requires data clear.
5. CSE_UPDATE_METADATA_ERROR: Unable to read CSE metadata from CBFS.
This change also prepares the file for follow up changes which
completely drop cse_rw_metadata structure.
BUG=b:184892226
Change-Id: Iabecab8e373e65a11ba7fe1bfc125467571a0588
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58157
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently WWAN_AUX_RST_L is in S5 domain and does not get asserted on
S0i3 entry. Based on the schematics, the pull-down on that signal leads
to 10 mW power leakage on S0i3 entry. Assert the signal on S0i3 entry to
achieve some power savings and de-assert it on S0i3 exit.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the signal gets
asserted on S0i3 entry and de-asserted on S0i3 exit. Trigger
suspend/resume cycles and ensure that the WWAN module is enumerated
after each cycle.
Change-Id: I43c8655ee5209779748e4365db973e094cb08aca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to handle S0ix entry and exit notifications by adding the
corresponding _DSM functions. The function indices are chosen based on
the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside
the notification functions perform any mainboard specific S0ix entry and
exit actions.
BUG=b:195748540
TEST=Build and boot to OS in Guybrush. Ensure that the notification
functions are invoked on S0ix entry and exit. Perform suspend/resume
cycles for multiple iterations.
Change-Id: I3014551f6e281d466628559453a0141a3dd6abad
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Init overridetree based on the schematics.
Refer to brya0/overridetree.cb to update the settings of the devices
including DPTF, WIFI, NAU8825 and etc.
Refer to kano/overridetree.cb to update the SSD settings (pcie4_0).
TODO: DPTF and USB positions will be further updated later.
BUG=none
TEST=Build Pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I30d26a47fe93736c63b578c9180b148ef73e8b9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
HPD event may not be ready when configuring TCSS mux for DP,
check if any DP device is connected and wait for HPD ready before
TCSS configuration. Remove unnecessary dependency on mainboard
functions, use generic interface which provides USB-C mux
operations.
BUG=b:192947843
TEST=select ENABLE_TCSS_DISPLAY_DETECTION in Kconfig.name for
Brya. Build coreboot and update your Brya. Boot Brya with USB-C
display connected, you should find `HPD ready after %lu ms` and
`Port C%zd is configured to DP mode!` in coreboot log. Display
should show screen in developer mode or recovery mode.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Ia7e6dd952d3183ecb76de6d4887ee573ef89bb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently override speed config is applied only for non EM100 cases.
For EM100 case, override speed board version defaults to 0 leading to
"comparison of unsigned expression >= 0 is always true" error. Fix this
error by defining the override speed config for both EM100 and non-EM100
use-cases.
BUG=None
TEST=Build Guybrush for both EM100 and non-EM100 cases.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id8ee7b01c69c4555d6e6a7b0d5f095ea3aaf3405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58309
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
P_BLK is legacy and superseded by ACPI _CST. Also, the implementation
for most platforms in soc/intel is broken. Thus, drop it.
For APL the IO redirection is kept since it's used as replacement for
the broken MWAIT instructions.
Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add support to override SPI fast speeds based on board version from both
bootblock and verstage. Overrides apply for Guybrush only and SPI speed
is overridden from 66 MHz to 100 MHz starting board version 4. This will
help to improve the boot time on board version by ~60 ms and still allow
the old boards to boot with 66 MHz.
BUG=b:199779306
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5bf03ab8772f27aca346589e9c5662caf014d0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add support to override SPI ROM fast speed based on board version. This
will allow boards to start at lower speeds during bringup and then
switch to higher speeds after assessing the signal integrity. Also
implement a default no-op override.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.
BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.
BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the GPIO mux/control MMIO regions are within the ACPIMMIO region,
we need to call enable_acpimmio_decode_pm04 here first so that accessing
the GPIO registers will work.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I4bc076261c72cf999a5f2464b74cff6bf694d473
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There is the wrong register offset printed in the debug log when the
data register is written:
'lpc_tpm: Write reg 0x18 with 0xnn' should be
'lpc_tpm: Write reg 0x24 with 0xnn' for data FIFO access.
This can be confusing when searching for issues with the help of the
TPM debug messages since the code itself is correct. Fix this error.
Change-Id: Ic28ee5a07146e804574b887ea05c62e7e88e9078
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some poppy variants did not select a system type, which led to the
default desktop type being set. Select the best fit enclosure type
for each variant.
Alphabetize the variant-specific options for improved readability.
Change-Id: I7c23f8fa3ae1de67f7a68b8a4e9ec16c4e8044df
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Make use of the newly introduced ACPI macros for CPPC table generation
that currently exists of a bunch of confusing assignments of structs
that only get partially filled.
Test: dumped SSDT before and after do not differ.
Change-Id: I844d191b1134b98e409240ede71e2751e51e2159
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The preferred location for the SPD data on mc_ehl based boards is the
HW-Info data structure. Inside this structure there is a field of 128
bytes available for the SPD data. So in order to use it construct a
buffer in memory which is 256 bytes long (as FSP requests minimum 256
bytes for the SPD data) and where the upper 128 bytes are taken from
HW-Info holding the needed timing parameters for LPDDR4.
If there is a case where HW-Info is not accessible or where the
contained SPD data is not valid (by checking the CRC in HW-Info SPD)
fall back to fixed SPD data set in CBFS.
Change-Id: I2b6a1bde0306ba84f5214b876eaf76ca12d8f058
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
For 1 bit long bit fields an unsigned type should be used. In this case
uint32_t is used instead of a generic unsigned int for both consistency
reasons with the rest of the file and to clarify that the bits will be
packed into a 32 bit memory location.
TEST=Resulting image of a timeless build for google/guybrush results in
identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic630d1709174d90336746bc37da504437c12643c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
coreboot normally owns PCIe resets for all Cezanne based systems.
However during S0i3 resume coreboot cannot intervene for S0 GPIOs
(S5 carry over fine) so we needed an alternate way to de-assert
this reset on guybrush. This change feeds in the given S0 reset
GPIO (69 in this case) so that SMU may de-assert this reset on
S0i3 resume.
BUG=b:199780346
TEST=With latest FSP verify SD device trains each of 10 cycles
Cq-Depend: chrome-internal:4157948
Change-Id: Ieee31651db30147fda84ee1aa31df7cb1c206356
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58198
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as
specified in the DXIO descriptors. This change requires FSP version
1.0.4 revision 2 otherwise setting this value does affect any FSP
behavior.
BUG=b:199780346
TEST=Verify toggling this value is reflected in FSP
Cq-Depend: chrome-internal:4170351
Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Document what setting the PM_ACPI_S5_LPC_PIN_MODE and
PM_ACPI_S5_LPC_PIN_MODE_SEL bits causes. The corresponding code will
eventually be factored out and moved to the Cezanne SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I10e3eee5cfc1c5ba2c88b8b7e83e96e481f787e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since the LPC_LDRQ0_PD_EN gets set right after it got cleared, we can
remove the clearing of that bit. This is split off from the previous
patch to be able to use timeless build to verify that the previous patch
didn't change any behavior.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb300e7c7ce7e74c32ebdade0360ee4bd499b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It's hard to understand what this code is doing because it uses hard
coded values, so use the register and bit defines instead.
BUG=none
TEST=Timeless build for guybrush results in identical binary.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d74ed3b9b4984ab1e2a22c50375baf9c9589df0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
