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Author SHA1 Message Date
Angel Pons
37cae54034 nb/intel/x/bootblock.c Revert include <arch/pci_io_cfg.h> 
This partially reverts:

- Commit 77d3b655ed
- Commit 487c1a24f5
- Commit 875c21f491
- Commit c4d1b47ad9
- Commit b96c358751
- Commit 9cbf26d18e

It is intentional to use <device/pci_ops.h> whenever one needs to use
PCI config access. The bootblock.c files needing I/O config do not need
to be an exception to this.

Change-Id: Ifba05717dad404a844618815c5347a05e07a3362
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2021-02-04 10:21:06 +00:00
Francois Toguo
522e0dbdaa acpi: Add support for reporting CrashLog in BERT table 
Crash Data are collected and sent to the OS via the ACPI BERT.

BUG=None
TEST=Built, and BERT successfully generated in the crashLog flow.

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I00e390d735d61beac2e89a726e39119d9b06b3df
Signed-off-by: Nikunj A. Dadhania <nikunj.dadhania@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-04 10:21:02 +00:00
Nick Chen
5f30ae3714 mb/google/volteer: update thermal table for Eldrid 
1. Add pl4 value
2. Change policies passive with sensor 0 and 1
3. Change granularity value with pl1 and pl2

BUG=b:178768749
TEST=make buildall

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I2f1fe9a6de4dbb587b79cb8758c5458a3ae5d768
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50111
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 10:20:28 +00:00
Angel Pons
20ca7ebe31 mb/prodrive/hermes: Use some board settings from EEPROM 
Cache the board settings in memory to avoid having to read them from the
EEPROM multiple times. For now, configure the following settings:

- DeepSx
- USB power in S5
- Power state after G3

Change-Id: Id88529a0b064c54fdf341de3856a8877109d4b14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-04 10:19:33 +00:00
Angel Pons
7c7e9a2f16 mb/prodrive/hermes: Define board settings in EEPROM 
Hermes has an EEPROM with firmware configuration data. Add definitions
to read and verify the `board settings` from the EEPROM. Subsequent
commits will hook up these EEPROM settings.

Change-Id: Id86632192ae53fd6b0e4df5b26b5a0a81e972818
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-02-04 10:19:26 +00:00
Sunway
fe97ee33e8 mb/google/kukui: kakadu: update the initial code for BOE LCD 
The latest initial code is from BOE, the vendor.

BUG=b:179206650
BRANCH=kukui
TEST=Run long time aging test and the BOE LCD shows normally.

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: Ibc1bd5147dbda4e3b94023e7ba52ff6a18abba0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50215
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 10:19:17 +00:00
Elyes HAOUAS
3b3d085338 src: Remove useless comments in "includes" lines 
Change-Id: Ide5673dc99688422c5078c8c28ca5935fd39c854
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-02-04 10:18:49 +00:00
Angel Pons
b3fcd5d57c soc/amd/picasso: Fix copy-paste error in macro definitions 
The `_MASK` macros should be using the corresponding `_SHIFT` macros.

Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-04 09:55:33 +00:00
Elyes HAOUAS
7080856542 mb/clevo/cml-u/bootblock.c: Remove unused includes 
Change-Id: I048e906306bf77a941b5f731ade15292fa944390
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-04 09:54:35 +00:00
Elyes HAOUAS
c351e8c302 mb/amd/{parmer,thatcher}/bootblock.c: Remove unused includes 
Change-Id: I4d5520649addc671527e75f9090ea45a83b5db9b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-02-04 09:54:18 +00:00
Mathew King
9a2b5e0ca3 mb/amd/majolica: add fmd for use when building chromeos 
BUG=b:177909472
TEST=builds

Change-Id: I5eb3c60fe60e4029485fae642c88c5c013ffb3f6
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50208
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 09:54:04 +00:00
John Zhao
21e2b5a0ce soc/intel/tigerlake: Drops 100ms delay in TBT PCIe root ports _PS0 
A minimum of 100ms delay is required before sending a configuration
request to the downstream components. Since the kernel already adds
100ms, this change drops the extra 100ms delay in TBT PCIe root ports
_PS0 method in order to improve resume time.

BUG=b:177519081
TEST=Boot to kernel and validated various tests on Voxel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic392f9af6cd739507a80a4ca3fd126088b513304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50086
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 09:53:15 +00:00
Patrick Rudolph
cfa02256a5 mb/emulation/qemu: Fix SMP boot 
Fix booting with SMP enabled, when specifying more CPUs than supported
by the code.

Change-Id: Ib3d7c1a1a7a8633d4d434ccbd46cf92b0074b724
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-02-04 09:53:02 +00:00
Elyes HAOUAS
944da4828f src: Remove unused <bootstate.h> 
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
 2021-02-04 09:51:10 +00:00
Elyes HAOUAS
865db966f8 src: Remove unused <cbfs.h> 
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-04 09:50:53 +00:00
Elyes HAOUAS
560384fe96 soc/qualcomm/sc7180/aop_load_reset.c: Add missing <program_loading.h> 
Change-Id: Ibb4bf488d9398240bf54f12b5b90d0f2a5a9119b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50196
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 09:50:41 +00:00
Elyes HAOUAS
a11675c42b soc/mediatek/mt8192/spm.c: Add missing <string.h> 
Change-Id: I56a4e0fb42c881026f4ee1abe30f9b356af6a68f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50168
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 09:50:28 +00:00
Kyösti Mälkki
64120762f8 coreboot_table: Move VBOOT_VBNV support 
The guard changes from (CHROMEOS && PC80_SYSTEM) to
VBOOT_VBNV_CMOS here.

Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-02-04 08:43:39 +00:00
Subrata Banik
3d93f045b2 vc/intel/fsp/fsp2_0/alderlake: Add required macros into MemInfoHob.h 
The recent merge of Intel ADL FSP 2017.00 appears to have introduced a
new dependency within the file MemInfoHob.h. Adding required macros to
resolve the dependency.

BUG=b:178846328

Change-Id: I18370edca481bac5fdd483680cd7b05b216d10fc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:34:15 +00:00
Kyösti Mälkki
43881bb214 mb/google: Convert some CONFIG(CHROMEOS) preprocessor 
Change-Id: Ica8691e3dc4feecbeb11ba3f5868932f926965b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:08:17 +00:00
Kyösti Mälkki
864be5bae5 mainboards: Remove default CHROMEOS=y 
Even the boards with MAINBOARD_HAS_CHROMEOS need to be build-tested
with CHROMEOS=n.

Change-Id: I16fcf62a23dae1b21c77cee275c867f9c1de893b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-02-04 07:03:44 +00:00
Kyösti Mälkki
dc15505795 vc/google/chromeos: Drop <acpi/vpd.asl> 
This was used as a means to read the MAC address and dynamically
return it to the ethernet driver via ACPI. The kernel team ended
up going another direction so this became obsolete.

Change-Id: I7065bea4b288c689b41cc969989ec6fd87c75f1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49902
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:02:03 +00:00
Kyösti Mälkki
07bce4ba36 coreboot_table: Convert some CONFIG(CHROMEOS) preprocessor 
Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48786
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 07:00:32 +00:00
Kyösti Mälkki
563c860c0f coreboot_table: Drop <vboot/misc.h> include 
Could have been removed with commit 63b9700b2c already.

Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 06:59:54 +00:00
Kyösti Mälkki
368c9a1847 vc/../chromeos.asl: Drop CHROMEOS guard 
coreboot proper now has a single include for this file
with the guard around it already.

Change-Id: Ice48a6af391170232a0319cc894bdb6c465c5143
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-02-04 06:58:51 +00:00
Felix Held
65fd33f95f vendorcode/amd/fsp/cezanne: add UPD structs from FSP build 
There will be incompatible changes during the further development of the
coreboot+FSP support for Cezanne, but we do need the FSP-M UPD struct
size to match the one in the FSP header. See CB:50241 for details.

Signed-off-by: Justin Frodsham <justin.frodsham@protonmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icade1d7bcab7b85cdd25c4114590eb23b914edcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50242
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-04 01:36:04 +00:00
Felix Held
c0dbd4cb56 soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers 
Picasso has 32 configurable GPEs, not only 28.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-04 00:10:20 +00:00
Felix Held
404aea866c amd/common/block/acpi/pm_state: fix comparison in get_index_bit 
In the case of passing 32 as limit the code returned -1, but should have
continued, since 32 is a valid value here.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ca341841bad62abcb4ea26a350c539813a29de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-04 00:10:02 +00:00
Wayne3_Wang
585f4d46cc mb/google/volteer/variants/drobit: Configure USB2 port for Type-C 
USB2 ports assigned to type-C connector need to be configured properly
by the USB2_PORT_TYPE_C. and also modify the description of USB port.

BUG=b:177480902
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the typeC port function is normal by manual.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: I9e962f8cd76e1986700821168594c50bc21553e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50217
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 20:11:40 +00:00
Derek Huang
ed6bda2818 soc/intel/tgl: Add configurable value for ConfigTdpLevel 
According to Tigerlake TDP specifications (doc #575683, table 4-2),
TGL supports different TDP levels depends on CPU segement/package,
IA Cores and graphics configuration. For example, UP3 4-Core GT2
suppots base TDP=28W, Configurable TDP-Down_1=15W and Configurable
TDP-Down_2=12W. This configurable value can be used to select
suitable TDP level

Change-Id: I4242575807caac172b6cbe667839bf6c9241f3c5
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-02-03 20:11:06 +00:00
David Wu
e65e9dd6b1 mb/google/volteer/var/voema: Enable EEPROM for OV2740 
Add ACPI entries for AT24 NVM device.

BUG=b:169551066
TEST=Build and run for basic camera functions.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib8fb684166649f78713050d62445bf47189b06ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jim Lai <jim.lai@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 20:04:59 +00:00
Felix Held
ee1fb0aa1a soc/amd: rename sb_init_acpi_ports to fch_init_acpi_ports 
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 20:00:48 +00:00
Felix Held
70f1af8934 soc/amd/cezanne: remove UART2/3 AOAC device offsets 
UART2 and UART3 don't exist on Cezanne which now has been verified, so
remove the corresponding AOAC offsets.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67755bd34df3a835cc39929bdc24f711d158b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-02-03 19:59:54 +00:00
Chris Wang
4c4a360018 soc/amd/picasso: clean up and re-sort UPD table 
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.

remove:
	EDpPhySel
	EDpVersion
rename:
	DpPhyOverride -> edp_phy_override
	EDpPhySel -> edp_physel
	DpVsPemphLevel -> edp_dp_vs_pemph_level
	MarginDeemPh -> edp_margin_deemph
	Deemph6db4 -> edp_deemph_6db_4
	BoostAdj -> edp_boost_adj

eDP phy setting:
    DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
    COMMON_MAR_DEEMPH_NOM = 0x004b
    COMMON_SELDEEMPH60 = 0x0
    CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-02-03 17:27:30 +00:00
Zhuohao Lee
275440edf1 mb/google/volteer/variant/copano: support regular/numpad touchpad 
Define the 25th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

BUG=b:174027837
BRANCH=firmware-volteer-13672.B
TEST=build pass

Change-Id: Ic5d61f19fd385600cfdcdd045dab1e61b06e4663
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 17:23:05 +00:00
Subrata Banik
c5cc741fe9 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 2037 
List of changes:
1. FSP-M Header:
- Adjust Reservedxx UPD Offset
2. FSP-S Header:
- Adjust UPD Offset for Reservedxx

Change-Id: I808cf619f43e629c6150726f2aa29e732e05fc33
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 15:50:10 +00:00
Zheng Bao
b993cb2d6c amdfwtool:cezanne: Add entry of PSP_BOOTLOADER_AB (0x73) 
Change-Id: Ie3577b403c1de7f20b6d5bcf9e1a5d47450266fe
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-02-03 13:48:51 +00:00
Pablo Stebler
a5ce4d3e68 ec/hp/kbc1126: Wait a longer time after sending 
This fixes the fan always running at full speed on ProBook 6360b,
EliteBook 8470p and ProBook 640 G1 (because the fan control command was
not sent).

On the ProBook 6360b, the EC needs about 30 ms to process the first
command on a cold boot, but other models such as the ProBook 640 G1 need
more time.

Change-Id: I8623af75c062d6aa69d4412e0627d426c69019fb
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-02-03 11:52:44 +00:00
Nico Huber
19dd694401 pci_ids/intel: Add missing CFL-S GT1 IGD IDs 
Change-Id: I372b6b2d602dfe116d5791bb6a6653454523b42b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
 2021-02-03 08:58:39 +00:00
Nico Huber
1b5e855347 pci_ids/intel: Correct 0x3e96, it's a CFL-S part 
Change-Id: Ibdddb3309f862f52c578e91ba3dc310dff8f70bc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-03 08:58:33 +00:00
Elyes HAOUAS
39df11f104 src: Remove unused <boardid.h> 
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
 2021-02-03 08:56:39 +00:00
Elyes HAOUAS
0322bc5ed8 src: Remove unused <cbmem.h> 
Change-Id: I2279e2d7e6255a88953b2485c1f1a3b51a72c65e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-02-03 08:56:35 +00:00
Elyes HAOUAS
a684d677fb soc/ti/am335x/header.c: Add missing include 
Use of 'offsetof' needs <commonlib/bsd/helpers.h>.

Change-Id: Ie250b20f464909649b2bd038dbb757d5df637486
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:55:15 +00:00
Wayne3_Wang
49e1140879 mb/google/volteer/variants/drobit: Modify touchpad I2C sequence 
Modify touchpad I2C sequence to meet requirement.

BUG=b:178512111
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the touchpad I2C5 sequence by EE.

Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Iebbeeec51b802c318ac014dcdd2603b600d931a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49958
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:54:54 +00:00
Wayne3_Wang
df7d4fc297 mb/google/volteer/variants/drobit: Add TBT PCIE rp setting for drobit 
Add the TBT PCIE rp setting to on and also fixes system hang
in recovery screen after selected "Power off" item problem.

BUG=b:177963941
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot chromeos-bootimage
     build Pass
     And check the system can power off normally in recovery page

Cq-Depend: chrome-internal:3581043
Signed-off-by: Wayne3_Wang <Wayne3_Wang@pegatron.corp-partner.google.com>
Change-Id: Ic0a4756b4af839ea0a23febb991bd71af7733dcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50103
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:54:41 +00:00
Johnny Lin
a70ebdf289 intel/xeon_sp: Select TPM_STARTUP_IGNORE_POSTINIT if INTEL_TXT is selected 
Because ACM already does TPM initialization.

Change-Id: I49cc3b0077b220b0ca0bfa048be1e3d3d7023b05
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-02-03 08:54:02 +00:00
Neill Corlett
ed7ebc26fa hatch: Update fan and thermal settings for ambassador 
Update fan and thermal settings for ambassador, per recommendations from
Quanta.

BUG=b:177765580
TEST=Built AP firmware

Change-Id: I080859f872caf696f0c085defb8372de658da58a
Signed-off-by: Neill Corlett <corlett@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50100
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Joe Tessler <jrt@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:53:41 +00:00
Elyes HAOUAS
3cf3635d23 mb/biostar/th61-itx/early_init.c: Clean includes 
Change-Id: I0619e567527812bd0e7088d23d91f114c8fec9ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-02-03 08:53:27 +00:00
Patrick Rudolph
dec2c78403 drivers/aspeed: Fix some issues 
* Use probe_resource instead of find_resource. This prevents
  a call to die and instead returns NULL.
* Handle the case where BAR2 isn't present
* Don't hardcode legacy VGA when BAR2 is present. This fixes
  graphic initialisation when the Aspeed isn't the primary GPU
  and thus doesn't decode VGA cycles.

This makes the coreboot code more similar to the Linux kernel code.

Change-Id: I2a99712a562a57c65f1cd0df7b1d7606681afe9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50195
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-02-03 08:53:10 +00:00
Angel Pons
6d7a6d291d mb/google/sarien: Turn hda_verb.h into hda_verb.c 
Change-Id: I40c8145fdddf9605bc3cc66ae8075e52dca4e539
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-02-03 08:52:35 +00:00