44da9e73c7
sb/intel/i82801gx,ix,jx: Move HAVE_SMI_HANDLER conditional
...
Make these more consistent with later platforms. Followups will
do a more complete refactoring of set_acpi_mode() implementations.
Change-Id: I6a05b7600ebdc49915157eaff229459a1eea754c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-13 21:15:13 +00:00
cd0b67b30a
sb/intel/i82801dx,ix: Replace SMM_ASEG conditional
...
PARALLEL_MP path also calls smm_lock().
Change-Id: I270fc8266d118cd1e7245ea70b707a03aedac209
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-13 21:13:39 +00:00
7630803b85
sb/intel: Remove ENABLE_ACPI_MODE_IN_COREBOOT
...
Change-Id: Ic807f4b4fc26232301f81c8076daf31fe58f217b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-13 21:10:08 +00:00
a7fb23081c
arch/x86: Correctly determine number of enabled cores
...
Instead of using MAX of (cores_enabled, MAX_CPUS), use MIN
which is correct.
TEST=tested with dmidecode
Change-Id: Id0935f48e73c037bb7c0e1cf36f94d98a40a499c
Signed-off-by: Andrey Petrov <anpetrov@fb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: David Hendricks <david.hendricks@gmail.com >
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-13 19:11:39 +00:00
a2d123ea98
nvidia/tegra210: Enable RETURN_FROM_VERSTAGE to free up space
...
All stages on this board are very close to the limit, so enable
RETURN_FROM_VERSTAGE so that we can overlap verstage and romstage to
use the available SRAM more effectively. (Coincidentally, this also
reduces verstage size quite a bit... maybe we should consider just
making this the default at some point, there are really no downsides.)
Change-Id: I2b91fd13d147f964bcbd7b2850f8a0931ea060df
Signed-off-by: Julius Werner <jwerner@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2019-11-13 09:39:27 +00:00
87074f9042
sb/intel/i82801jx: Enable upper 128bytes of CMOS
...
The normal romcc bootblock uses this.
Change-Id: I60f735f703a9208911f5cc8a81930535e574644d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36755
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-13 09:22:50 +00:00
dc972e17c7
nb/intel/x4x.h: Include stdint.h
...
The structs and function definition in that header require it.
Change-Id: I3466ff1a28459d0285e27d368314faf747e2eac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2019-11-13 09:15:59 +00:00
b236352281
sb/intel/i82801gx: Add a function to set up BAR
...
This removes some of the sb code in the nb.
Change-Id: I2ab894be93f210220fa55ddd10cd48889f308e5b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2019-11-13 09:14:20 +00:00
0d92271d2c
spi: Add Winbond W25Q128JW_DTR SPI ROM support
...
BUG=b:144297264
TEST=Boot with W25Q128JW_DTR and check MRC data save/restore works.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com >
Change-Id: Ica6344556e5de94555b95dd7c6df5600614811e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
2019-11-13 09:13:25 +00:00
ead8a07cee
intel/82801dx,ix: Rename SMM_ASEG functions
...
Static declarations for use with SMM_ASEG conflict those
declared globally for use with SMM_TSEG.
Change-Id: I8d2984cd8fe6208417b2eda0c10da8fc7bb76cf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35892
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-13 09:12:10 +00:00
799184397a
mb/google/hatch/variants/helios: Fix leakage voltage problem on touchscreen
...
Set GPP_C4 default to low to fix leakage voltage problem on touchscreen during power on.
BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com >
Change-Id: Ie9197192c9d6dfb30c10559990c6010b1b2d3a45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Shelley Chen <shchen@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-13 05:02:33 +00:00
87c52809b2
lib/bootmem: Correct error message
...
bootmem_allocate_buffer() displayed "unitialized", this is changed to
"uninitialized".
BUG=N/A
TEST=build
Change-Id: I84ae689ddb24f3e3d2387735faf3850e6bd6dfa9
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-11-12 18:29:16 +00:00
c6872f5524
soc/intel/tigerlake: Remove FSP-T option in Kconfig
...
This code lacks the temp_ram_init_params sybols so the FSP-T option
so it would fail to build.
Change-Id: Ie7d75943d89a964d0189f921fc433e4b9adfb0c5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Michael Niewöhner
2019-11-12 18:28:52 +00:00
b6768370d1
soc/intel/icelake: Remove FSP-T option in Kconfig
...
This code lacks the temp_ram_init_params sybols so the FSP-T option
fails to build.
Change-Id: I2b6278bd64a3579ed3460af39ea244c7dfd51da4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Michael Niewöhner
2019-11-12 18:28:45 +00:00
cd3c3167df
mainboard/google/hatch: Create helios_diskswap variant
...
Created helios_diskswap as a variant of helios (hatch variant).
BUG=b:143378037
BRANCH=None
TEST=none
Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177
Signed-off-by: Alexis Savery <asavery@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2019-11-12 18:28:07 +00:00
df9cdcfc38
arch/x86/car.ld: Rename suffix _start/_end
...
This is more in line with how linker symbol for regions are defined.
Change-Id: I0bd7ae59a27909ed0fd38e6f7193816cb57e76af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-11-12 18:25:42 +00:00
fee2fdecc2
/mb/google/hatch: add new memory config support
...
1. Add 16G 2666 2 bank group
2. Add 16G 3200 4 bank group
BUG=b:142762387
TEST=boot with memory (KAAG165WA-BCT/H5ANAG6NCMR-XNC)
Change-Id: I04810091ef2bf8ec1bd306ad141a70436638eac8
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2019-11-12 18:25:14 +00:00
996588521a
src/mainboard/siemens: Use PTN3460 chip driver
...
This patch replaces and cleans up the redundant PTN3460 driver files in
/mainboard/siemens directories by using the now available driver in
src/drivers/i2c/ptn3460 and providing mainboard specific functions to
the driver.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: I976a502e7176a356bab772758250db3cdff529b9
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36643
Reviewed-by: Werner Zeh <werner.zeh@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-12 18:24:31 +00:00
11a34ec4c2
drivers/i2c/ptn3460: Provide chip driver for PTN3460
...
This patch provides a chip driver for the DP-2-LVDS bridge PTN3460.
The bridge is configured via I2C. As the mainboard has all the
information regarding the attached LCD type, there are three hooks into
mainboard code to get the information like EDID data and PTN config.
TEST=Display is working on Siemens mainboards (e.g. mc_tcu3, mc_apl1, ...).
Change-Id: Ie4c8176cd16836fa5b8fd2f72faf7a55723b82f6
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Werner Zeh <werner.zeh@siemens.com >
2019-11-12 18:24:19 +00:00
c484da1a98
sb/intel/i82801jx: Add common code for LPC decode
...
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-11-12 18:23:07 +00:00
fecf77770b
sb/intel/i82801gx: Add common LPC decode code
...
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-11-12 18:22:57 +00:00
675cb9152e
util/autoport: Stop generate empty h8_mainboard_init_dock().
...
CB:36385 makes dock init in ramstage fully mainboard-specific, so
keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes
unnecessary and problematic.
Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83
Signed-off-by: Bill XIE <persmule@hardenedlinux.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2019-11-12 18:22:34 +00:00
8088584b37
payloads/external/GRUB2: Check for existing grub2 directory
...
When 'make clean' is executed and there is no source code cloned for
GRUB2 in payloads/external/GRUB2/grub2 (so GRUB2 has never been used on
this tree) an error message is thrown:
"fatal: cannot change to 'grub2': No such file or directory"
This error happens when there is no grub2 directory and is caused by
line 20 in payloads/external/GRUB2/Makefile where a shell command is
used to check the state of the git repo for grub2. Thought the target
for this code (checkout) is not executed by 'make clean' the shell
evaluates the command as part of the Makefile sourcing and encounters a
missing directory.
This patch fixes this error by checking for the project directory before
the git status of the repo is evaluated.
Change-Id: Ieaa919e1ee5ec2a1ec3c840fa07a6ec16d230e88
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2019-11-12 18:22:19 +00:00
1b8102474e
mb/siemens/mc_apl6: Enable VT-d feature
...
This mainboard needs VT-d to be enabled. Do so in devicetree.
Change-Id: I9f2f733163be019ac329660d7633b48c5d7896f1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
2019-11-12 18:21:57 +00:00
71a94301c0
Documentation: Add more entries to 4.11 release notes
...
Change-Id: I1b013c4d7012f1db9591bea98ec1fe7acbc85afe
Signed-off-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36751
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-12 18:21:45 +00:00
8a0dccc02b
vendorcode/intel/Kconfig: Hide UDK_VERSION when unneeded
...
This cleans .config from unused UDK_VERSION's symbol.
Change-Id: I2a17db711f615d388dbd964f67ff2cc7875c54fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34536
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-12 12:20:16 +00:00
6de0c141fd
soc/intel/tigerlake: Remove deprecated CONFIG_SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
...
CB:36620 moves common cbmem_top_chipset to fsp driver hence no need to have
dedicated kconfig as in SOC_INTEL_COMMON_BLOCK_SA_FSP_TOLUM
Change-Id: I3914993754ba409867399e903e5d13e929a92e1d
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: V Sowmya <v.sowmya@intel.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-11-12 09:29:42 +00:00
de6f121897
mb/google/kukui: Add new configs 'damu' and 'kappa'
...
New boards introduced to Kukui family.
BUG=None
TEST=make # select damu and kappa
Change-Id: I7154aeee921114b7d12bf586adca250df19a3883
Signed-off-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2019-11-12 08:27:59 +00:00
72f13e534b
ec/lenovo/h8: Make dock init in ramstage fully mainboard-specific
...
Discussed in CB:36093, in the past many lenovo boards need to declare
an empty h8_mainboard_init_dock() to satisfy h8.c.
Now the confusing H8_DOCK_EARLY_INIT might be retired, and if a
mainboard needs dock init (done with h8_mainboard_init_dock() in the
past) in ramstage, (discussed in CB:4294 where H8_DOCK_EARLY_INIT is
introduced) it can just do it in its own chip_ops.enable_dev function.
Tested on X200. Testing on other affected targets may be necessary.
Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1
Signed-off-by: Bill XIE <persmule@hardenedlinux.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-12 08:26:42 +00:00
9764bc126e
mb/*: Fix default fmap with VBOOT_SLOTS_RW_A enabled
...
Don't select the VBOOT fmap as default if VBOOT is disabled.
Fixes a regression introduced by f8251b98siro@das-labor.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36707
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-12 08:25:45 +00:00
b7e8505d96
soc/{cannonlake,skylake}: Remove unused 'rdmsr(MSR_CONFIG_TDP_NOMINAL)'
...
MSR_CONFIG_TDP_NOMINAL is used by 'cpu_get_tdp_nominal_ratio' to return the
TDP Nominal Ratio.
Change-Id: I4c8df7a4100c185c1430d993f7618ed00fc556ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 22:44:24 +00:00
2384682565
soc/mediatek: Add missing '#include <console/console.h>'
...
Change-Id: I2e79ff3352fe974a070b7b3f5e4b5570ed2b294c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 22:40:57 +00:00
187655cee0
mb/{google/fizz,razer/blade_stealth_kbl}: Add missing include <console/console.h>
...
Change-Id: Ia4e496d359036591131c1ec0243d64c58823ca63
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 22:38:23 +00:00
77fe213b55
SMBIOS: Add 'CXL FLexbus 1.0' memory array location
...
Change-Id: Ib66616ddefe6254c7c64f223c4f3f7cc8d198bb7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 22:36:55 +00:00
898ca04fa4
AGESA: Select CBMEM_STAGE_CACHE with HAVE_ACPI_RESUME
...
Fix regression with commit 0a4457fkyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Mike Banon <mikebdp2@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 21:20:12 +00:00
f76c12a3fc
mb/asus/p5ql-em: Fix S3 resume
...
The superio VSBGATE# functionality needs to be enabled for ram to be
powered during S3.
Change-Id: I7b827e025de7d5b53c587872238a411fc9c2e762
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36709
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 21:19:16 +00:00
b8cd4b0049
drivers/intel/fsp2_0: move common cbmem_top_chipset to fsp driver
...
The common cbmem_top_chipset implementation uses the FSP bootloader HOB,
thus move it to the fsp driver which is a more appropriate place.
Change-Id: I914df51a7414eb72416f816ff8375a13d5716925
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36620
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: David Guckian
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 13:22:39 +00:00
46e68ac99a
soc/intel/denverton_ns: make use of common cbmem_top_chipset
...
This replaces denverton_ns's own implementation of cbmem_top_chipset and
selects the common code one.
Change-Id: Idae96aabe2807e465bb7ab0f29910757d0346ce9
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36619
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 13:21:02 +00:00
0cc619bedc
vendorcode/eltan/security/mboot/mboot.c: Correct parameter description
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The flags parameter of the tpm2_get_capability_pcrs() is used by
mboot_hash_extend_log().
BUGS=NA
TEST=Build
Change-Id: Ia718d27f21d41a5e16230c74ca402ea6099470b2
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2019-11-11 11:28:46 +00:00
a1c259beef
security/vboot: Add rw_region_only support to vboot
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In some case where the flash space is limited or when a large payload such as LinuxBoot
is used, the RO region may not be large enough to contain all components that would
normally be added.
This patch adds the possibility to add specific components to the RW regions only in
the same way as the RO_ONLY_SUPPORT does for the RO region.
Please note: this applies only to the items that would normally be added to all regions.
If the payload is directed to the RW region only, a recovery payload needs to be added
to the RO region manually.
BUG=N/A
TEST=build
Change-Id: Ie0df9b5dfc6df4f24efc5582a1aec9ecfb48c44d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36544
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 10:38:34 +00:00
02a4a0d471
soc/intel/tigerlake: Fix cbmem_top
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EBDA support was dropped.
Change-Id: I83d838b79e2653d4e3764cfc7deaca9bb241deab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36718
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 10:37:42 +00:00
9caadfe708
mb/siemens/mc_apl6: Add TPM to devicetree
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The TPM chip needs to be added to the devicetree so that the ACPI tables
will be generated for it. These ACPI table entry is used by the OS to get
the location of the TPM chip.
Change-Id: Ic40d1cf236dd849f04f088808d94b6dd81e3238a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
2019-11-11 10:35:17 +00:00
a4b7befbd5
mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller
...
This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.
Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 10:35:06 +00:00
4f7fe494a0
mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge
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On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.
Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
2019-11-11 10:34:55 +00:00
7c276c0dd7
mb/siemens/mc_apl6: Enable VBOOT per default
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mc_apl6 uses VBOOT scheme so enable it as default.
Change-Id: I341180f3815ff9f3b2db801d9d989119a2585b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
2019-11-11 10:34:36 +00:00
0dc87ef90d
mb/siemens/mc_apl6: Add new mainboard based on mc_apl3
...
This patch adds a new mainboard variant called mc_apl6 which is based
on mc_apl3. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Change-Id: Ic935f6cc1f037947b2c167696d40da8309e4d4f0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
2019-11-11 10:34:09 +00:00
6754dcda74
soc/intel/quark: make use of common cbmem_top_chipset
...
This replaces quark's own implementation of cbmem_top_chipset and
selects the common code one.
Change-Id: I445c471b654abfa922b20215e52a2794529be120
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 10:33:51 +00:00
97012bd019
soc/intel/apollolake: make use of common cbmem_top_chipset
...
This replaces apollolake's own implementation of cbmem_top_chipset and
selects the common code one.
Change-Id: I11d12a6c8414a98d38be8b0dbf6dc57cd2efc5d6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36618
Reviewed-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-11-11 10:33:11 +00:00
45ddb4344f
console,boot_state: Exclude printk() from reported times
...
Use monotonic timer to accumulate the time spent in
console code.
For bootblock and romstage, only stage total is reported.
For ramstage each boot_state is reported individually.
Change-Id: Id3998bab553ff803a93257a3f2c7bfea44c31729
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2019-11-11 10:31:29 +00:00
19825e8e37
Documentation: Add some significant 4.11 release notes
...
Change-Id: I0f9a5afe85068e6ef2a0b0d088557b0dd1e5bd91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-11-11 10:31:14 +00:00
