The fspNotify(EnumInitPhaseAfterPciEnumeration) is already
registered in fsp_util.c as a generic callback, this is some code
left from early development.
Also I don't see a need for the chip_final function, although we
could keep it as a placeholder but i decided to remove it.
BUG=chrome-os-partner:42979
BRANCH=None
TEST=build with current fsp and the coming fsp 1.3.0, boot on sklrvp3.
Change-Id: Ia892f2021be324859c344b4cb8cdeaf75f7ee32f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae22ad57ddbab787da000ae99f85fd2b3d4092e7
Original-Change-Id: I41be566da71f80451ff70ddd8ada77bf9b8d5b1d
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/287991
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11054
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add the files to support the Skylake SOC.
Matches chromium tree at 927026db
BRANCH=none
BUG=None
TEST=Build and run on a Skylake platform
Change-Id: I80248f7e47eaf13b52e3c7ff951eb1976edbaa15
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10341
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the Broadwell implementation as the comparison base for Skylake.
BRANCH=none
BUG=None
TEST=None
Change-Id: I22eb55ea89eb0d6883f98e4c72a6d243e819e6d8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10340
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
