Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread
on HyperThreading enabled platforms, to prevent race conditions and
resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Leverage already used eax register in bootblock_protected_mode_entry.
Avoid another register ebx just for preserving eax value as it is not
needed and is not used at all after moving the value into mm0.
Allow EBX to be preserved for other usage.
Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As code already used CBMEM hooks to switch from CAR to CBMEM
it was never necessary to have the structure declared inside
_car_relocatable_data.
Switch to use car_[get|set]_ptr is mostly for consistency, but
should also enable use of usbdebug with FSP1.0 romstage.
Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Keep track of the active timestamp table location using
a CAR_GLOBAL variable. Done this way, the entire table
can be located outside _car_relocatable_data and we only
switch the pointer to CBMEM and copy the data before
CAR gets torn down.
Fix comments about requirements of timestamp_init() usage.
Remove timestamp_cache from postcar and ramstage, as CBMEM
is available early on.
Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35032
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifd4329905847d9dd06de67b9a443c8ee50c0e7a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These platforms return to romstage from FSP only after
already having torn CAR down. A copy of the entire CAR
region is available and discoverable via HOB.
Previously, CBMEM console detected on-the-fly that CAR
migration had happened and relocated cbmem_console_p
accoringlin with car_sync_var(). However, if the CAR_GLOBAL
pointing to another object inside CAR is a relative offset
instead, we have a more generic solution that can be used
with timestamps code as well.
Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35140
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a generic SuperIO ACPI generator, dropping the need to include
additional code in DSDT for SuperIO.
It generates a device HID based on the decoded I/O range.
Tested on Supermicro X11SSH-TF using AST2400.
The SSDT contains no errors and all devices are present.
Possible TODOs:
* Add "enter config" and "exit config" bytes
* Generate support methods to enter and exit config mode
* Generate support methods to query, change or disable current
resource settings on specific LDNs
Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
tsc_freq_mhz() had a static table of Intel CPU families and crystal
clock, but it is possible to calculate the crystal clock speed dynamically,
and this is preferred over hardcoded table.
On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz
hence we had to use static table to calculate crystal clock.
Recommendation is to make use of CPUID.16h where crystal clock frequency
was not reported by CPUID.15h to calculate the crystal clock.
BUG=b:139798422, b:129839774
TEST=Able to build and boot KBL/CML/ICL.
Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They
don't benefit from having low-memory set as writeback-cacheable.
This also fixes regression from CB:34893 that caused some random
hangs with more recent intel SoCs in ramstage.
BUG=b:140250314
Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h,
respectively. That name is closer to the terminology used in most
functions related to Trusted Firmware, and it removes the annoying
auto-completion clash between arm64/arm_tf.c and arm64/armv8.
Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Also don't define the default as this result in spurious lines in the
.config.
The only difference in config.h is on boards with the Nvidia tegra210
SOC that now select ARCH_ARM64, because its ramstage runs in that
mode. The resulting binary is identical however.
Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many (if not all) platforms have moved to using consistent
boot flow constructs where a weak car_stage_entry() is no longer
necessary to avoid the complexity of handling the numerous and
different boot flow combinations. The weak symbol is just causing
issues so remove it.
Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Move descriptions below the license header
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Remove comments saying that a file is based on another file from the
coreboot project.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a new Kconfig symbol that allows an x86 device to begin execution
when its reset vector is in DRAM and not at the traditional 0xfffffff0.
The implementation will follow later, this is just to setup various
ENV_xxx definitions correctly for the build environment.
Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This enables the use of .bss section for ENV_BOOTBLOCK
and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y.
In practice, boards with CAR_GLOBAL_MIGRATION=y currently
build with romcc-bootblock so they will not be using .bss.
Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.
For consistency prefixes are changed from ARCH_ to ENV_.
Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
Note that the file include/arch/acpi.h is a fantastic example of why
moving to the authors file is needed. Excluding the guard statements,
it has 8 lines of copyrights for 3 function declarations.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I334baab2b4311eb1bd9ce3f67f49a68e8b73630c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34606
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Make sure files say that they're part of the coreboot project
- Move descriptions below the license header
- Fix some spacing
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id5f26a73f0df366651c076a94975bce1fb321b70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34605
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register exception handlers to avoid a Synchronous External Abort
that is raised when you try to access a non-memory address on ARMv8.
An exception handler can jump over the faulting instruction.
This is the feature only for QEMU/AArch64.
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: I09a306ca307ba4027d9758c3debc2e7c844c66b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Variable length arrays were a feature added in C99 that allows the
length of an array to be determined at runtime. Eg.
int sum(size_t n) {
int arr[n];
...
}
This adds a small amount of runtime overhead, but is also very
dangerous, since it allows use of an unlimited amount of stack memory,
potentially leading to stack overflow. This is only worsened in
coreboot, which often has very little stack space to begin with. Citing
concerns like this, all instances of VLA's were recently removed from the
Linux kernel. In the immortal words of Linus Torvalds [0],
AND USING VLA'S IS ACTIVELY STUPID! It generates much more code, and
much _slower_ code (and more fragile code), than just using a fixed
key size would have done. [...] Anyway, some of these are definitely
easy to just fix, and using VLA's is actively bad not just for
security worries, but simply because VLA's are a really horribly bad
idea in general in the kernel.
This patch follows suit and zaps all VLA's in coreboot. Some of the
existing VLA's are accidental ones, and all but one can be replaced with
small fixed-size buffers. The single tricky exception is in the SPI
controller interface, which will require a rewrite of old drivers
to remove [1].
[0] https://lkml.org/lkml/2018/3/7/621
[1] https://ticket.coreboot.org/issues/217
Change-Id: I7d9d1ddadbf1cee5f695165bbe3f0effb7bd32b9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
