Commit f1e401c6cb (util/cbfstool/flashmap/fmap.c: fix fmaptool
endianness bugs on BE) makes use of endianness conversion macros
in cbfstool's FMAP code, which is also used by ifdtool. At least
on Linux, the <endian.h> header provides these helpers, but only
when `__USE_MISC` is defined, which is defined in the <ctypes.h>
header when `_DEFAULT_SOURCE` is defined. This was accounted for
in `Makefile.inc`, but not in `Makefile`. As a result, trying to
build ifdtool as a standalone tool (i.e. not as part of building
a coreboot image) results in build errors because the endianness
conversion macros are not defined.
Define `_DEFAULT_SOURCE` in `Makefile` to fix the build errors.
Change-Id: I8c2bbc07ddd87d885e2d6f5c7f2bd501e5c4e3b0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59663
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
U-Boot normally runs with a display if available. Enable this option so
that the display shows if U-Boot supports it.
Use 'select' rather than 'imply' since the CI complains.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ie5684c6ead30076689f43034675ff9f3531970fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
At present the default ROM for for QEMU is too small for U-Boot to fit.
Add a condition to catch this and expand it to a 1MB ROM. This allows
booting U-Boot under emulation.
It also matches the size used by other emulation boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia1a8c1109e3ece5fec56255173a2d19d4a130bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The u-boot.bin file should be used, rather than u-boot-dtb.bin
While they are often the same, the -dtb version is really just for
legacy use now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I5558ed94c7dd6cc57ceb835fe367bfa050ad2150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This doesn't work at present, merely printing an error when U-Boot is
selected as a payload. This is because it adds a file into the U-Boot
tree which makes U-Boot's build system think that the tree is unclean.
Update the rules to put the tag file outside the source tree. Use an
out-of-tree build for U-Boot to avoid changing the source tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I24d6545b54f97afeefaca3ffed79eec2e7afacb4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).
BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIO_WAKE_* definitions are the ones that are used in the code, so
drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move
the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were
before this patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622673cc72107908b525a65212061062f32e13dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK,
GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code
so use those instead of magic numbers.
TEST=Timeless build results in identical image for amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding bit is marked as reserved in the following versions of
the documentation for all SoCs using this code:
Mullins: BKDG #52740 Rev 3.05
Stoneyridge: BKDG #55072 Rev 3.04
Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18
Raven2: PPR #55772 Rev 3.08
Cezanne: PPR #56569 Rev 3.03
The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as
PullUpSel, but this is no longer the case in newer versions. It is
unclear if this got de-featured or if it was never present in the
silicon. To be consistent with the current documentation, drop this
define.
This patch also change the definition of GPIO_PULL_MASK to only cover
the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a
default value of 0 for this bit after reset, so the resulting values in
the register aren't expected change. The other PPRs/BKDGs don't specify
a reset value for this bit, but it's likely safe to assume that all SoCs
that use the new GPIO interface use the same GPIO building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch moves common thermal API between chipsets
with thermal device as PCI device and thermal device behind PMC
into common file (thermal_common.c).
Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC
Kconfig to select as applicable for underlying chipset.
+------------------------------------------------------+--------------+
| Thermal Kconfig | SoC |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL |
| | till ICL |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards |
| | ICL |
+------------------------------------------------------+--------------+
Either of these two Kconfig internally selects
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Without manual handling, when 3rdparty/intel-sec-tools isn't around,
`make what-jenkins-does` reports only
go: go.mod file not found in current directory or any parent directory; see 'go help modules'
which isn't meaningful or actionable. Instead check that the go.mod file
exists and bail out with a better error message before trying to run
`go mod vendor`.
Change-Id: I035747746ca5fd54841bd67352044dde12a28185
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
There were escape backslashes around regular expression passed to grep.
Because of that, grep was returning empty results as a consequence of
pattern mismatch, and thus symbols pointing to original functions were
not created correctly.
Change-Id: I751109735b6c56824df9a560ae989bf062a0e9a6
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
