SKX FSP doesn't support X2APIC setup, but CPX does. The CPX DMAR
table needs the X2APIC opt out flag set. This fixes the hang loading
a kexec'd kernel. The change is easy to see in the coreboot output:
[DMA Remapping table] Flags: 0x3
or in the DMAR ACPI table.
Change-Id: Iec977c893b70e30875d9a92f24af009c1e90389e
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot. The fingerprint sensor was
previously left on, and was just powering down when the rails went low.
On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.
BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At this point, the zork platform will only use psp_verstage, so remove
the VBOOT_STARTS_IN_BOOTBLOCK option and set code for VBOOT_STARTS-
BEFORE_BOOTBLOCK to always be used.
TEST=Build & Boot Morphius
BRANCH=Zork
BUG=b:172848137
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I30d90fe82c37966a860b52c07a3550dcecf8d19d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Add the _HID INT33A1 to PEPD to make Linux recognize it as "Intel Power
Engine" in the pmc core driver.
The _ADR gets dropped, because _HID and _ADR are mutually exclusive.
Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
The PEPD enum function returns a bitmask to announce supported/enabled
PEPD functions. Add a comment describing this bitmask and correct the
return value to announce function 1, 5 and 6 as supported.
Also add comments to the disabled functions 3 and 4.
Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Windows does not comply with the Low Power Idle S0 specification and
crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does
not return at least one device constraint, even when function 1 is
announced as being not available by the enum function. Returning an
empty package does not work.
At least the following Windows versions were verified to be affected:
- Windows 8.1 x64, release 6.3.9600
- Windoes 10 x64, version 1809, build 17763.379
- Windows 10 x64, version 1903, build 18362.53
- Windows 10 x64, version 2004, build 19041.508
- Windows 10 x64, version 20H2 / 2009, build 19042.450
To make Windows work on S0ix-enabled boards, return a dummy constraint
package with a disabled dummy device.
Since the device constraints are only used for debugging low power
states in Linux and probably also in Windows, there shouldn't be any
negative effect to S0ix. Real device constraint entries could be added
at a later point, if needed.
Note: to fully prevent the BSOD mentioned above the LPIT table is
required on Windows, too. The patch for this is WIP, see CB:32350.
If you want to test this, you need to applie the whole ACPI patch
series including the hacky LPIT test implementation from CB:47242:
https://review.coreboot.org/q/topic:%22low_power_idle_fix%22
Test: no bluescreen anymore on Clevo L140CU on all Windows versions
listed above and S0ix gets detected in `powercfg -a`.
Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
PEPD function 2 is currently unused and disabled. Thus, drop the return
value, which matches the default return value.
Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
`ARG2` in the macro's names does not really provide any useful
information. Drop it and add `LPI` to clarify the relation to only
low-power idle states.
Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In
Device" and is the name Intel and vendors usually use, so let's comply.
Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Move the UUID to the condition, since there is no need to assign a name
when it is only used once. Also add a comment to make clear that the
functions inside that condition are only used by the Low Power Idle S0
functionality, while the PEPD in general can be present on boards
without S0ix capability, too. For details check CB:46469.
Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
PEPD will get included directly in the southbridge. Thus, drop the
scope around it.
Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
In the file uintptr_t that is defined in stdint.h and struct device that
is defined in device/device.h are used, so include them directly to
avoid having to rely on them being included in the file that includes
this header file.
Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The various platform BARs are not always the same size across different
SOCs, so use the defined size rather than a hardcoded value.
This results in the following change on TGL which increased the MCHBAR
size to 128K:
-system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved
+system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved
And fixes the following error output from the kernel:
resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff],
which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff]
Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.
BUG=b:171993054
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3
Add a NULL check and only skip setting the default operations
if `.ops` was set by a driver. It's fairly unlikely that some-
body adds a driver and forgets the `.ops` pointer. So this is
mostly to increase readability: Nobody should have to wonder
if we're missing a NULL-check.
The condition is moved out of the loop to reduce indentation
levels. Alternatively, we could jusk skip drivers that don't
have `.ops` set (i.e. continue the loop).
Change-Id: I5dcc05ebb092fb9c4be929c81ea2b05a10b1311b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46297
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices of class type "system" are arbitrary devices and it's not clear
which of them need bus mastering. Therefore, enable bus mastering
conditionally based on Kconfig option PCI_ALLOW_BUS_MASTER_ANY_DEVICE.
Change-Id: Ia04e83606a0a081c0758ec59e52627aa1dbd2622
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
If the stub size would be larger than the save state size, the stagger
points would overlap with the stub.
The check is placed in the stub placement code. The stub placement
code is called twice. Once for the initial SMM relocatation and for
the permanent handler in TSEG. So the check is done twice, which is
not really needed.
Change-Id: I253e1a7112cd8f7496cb1a826311f4dd5ccfc73a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47069
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
