Replace the dt option `PmTimerDisabled` with use of the Kconfig option
`USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer.
A default value representing the prior devicetree value was added to the
boards system76/{lemp10,galp5,darp7}, so this change will not alter
behaviour.
Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.
BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.
Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There are two different types of 282 SKU available with TDP
of 15W and 12W for Alder Lake-M SoC. This patch adds support
for these TDP values for 282 SKU as per document 643782.
BUG=None
BRANCH=None
TEST=Build FW and test on adlrvp board
Change-Id: I553b2362b7bf811e6bf02fd9d68f78c2caeb7398
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Use the get_supported_lpm_states() function to set the respective FSP
UPD.
TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.
This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.
BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.
Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design
BUG=b:184653645
BRANCH=None
TEST=compilation works fine and value of UPD is getting reflected.
Change-Id: I61faa661c12dced27c6cdd7005a61ae8de8621e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.
Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.
Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API
Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
