To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Clone entirely from Cannonlake
commit id: 3487095304
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>