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3516 Commits

Author SHA1 Message Date
Elyes HAOUAS
cfdcfdb515 src: Remove unused 'include <delay.h>' 
Change-Id: I6afea5c102299e570378a1656d3dcd329a373399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44093
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-18 12:19:18 +00:00
Mike Banon
d5ffa6e1b3 nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 
Required for adding the XMP profiles support. SPD buffer is
already 256 bytes at AMD AGESA vendorcode, so this is fine.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-17 07:13:05 +00:00
Elyes HAOUAS
a4dd33cc8b src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers 
Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-17 07:00:37 +00:00
Elyes HAOUAS
cf0f7ed3ee nb/intel/x4x/raminit_ddr23.c: Remove dead assignment 
Change-Id: I2da586abf63517a2e9b73ea4d3fab513370947bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-17 06:21:23 +00:00
Angel Pons
19c5cd210d nb/intel/sandybridge: Add comments to struct iosav_ssq 
Add the ranges of bitfields as comments on the struct.

Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
 2020-08-12 11:01:44 +00:00
Patrick Rudolph
4e0cd82b5b nb/intel/sandybridge/raminit: Add comments 
Add comments found when testing ECC scrubbing code.
This is a cosmetic change.

Change-Id: I7975f6070c2002930eec407a6b101a1295495b25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-11 12:03:09 +00:00
Patrick Rudolph
b5fa9c8200 nb/intel/sandybridge/raminit: Fix ECC scrub 
The scrubbing method was never correct nor tested.
Fix that by observations made on mrc.bin.

Tested on HP Z220 with ECC memory and Xeon E3 CPU:
The whole memory is now scrubbed.

Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-11 05:14:17 +00:00
Patrick Rudolph
d058131586 nb/intel/sandybridge/raminit: Add ECC debug code 
* Add ECC test code when DEBUG_RAM_SETUP is enabled
* Move ECC scrubbing after set_scrambling_seed() to be able to observe
  what has been cleared in the test routine. If clearing happens
  before set_scrambling_seed the data is XORed with a different PRN.
  Data read from memory will look random instead of all zeros.
* ECC scrubbing must happen after dram_dimm_set_mapping()
  The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In
  normal mode the ECC bits are calculated and stored on write
  transactions.
* Move method out of try_init_dram_ddr3().
  This satisfies point 2 and point 3 of the list above.

Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-08-11 05:14:01 +00:00
Angel Pons
b5f9e5ce83 nb/intel/sandybridge: Drop inexistent device from DMAR 
There's no `function 1` on the iGPU device for this northbridge.

Change-Id: I597446f703165447c3a0d0c1536583b08bc8450c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-06 11:16:46 +00:00
Angel Pons
8bf197653f nb/intel/sandybridge: Deduplicate PCIEXBAR decoding 
We can use `decode_pcie_bar` instead, as other northbridges do.

Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-06 10:57:39 +00:00
Angel Pons
20905cfe26 nb/intel/sandybridge: Refactor get_pcie_bar 
Turn it into `decode_pcie_bar`, taken from gm45.

Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-06 07:25:25 +00:00
Subrata Banik
b7db12bf7e {nb,soc}/intel: Use get_current_microcode_rev() for ucode version 
This patch removes all redundant read microcode version implementation
from SoC directory and refer from cpu/intel/microcode/microcode.c file.

TEST=Able to get correct microcode version.

Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-05 15:36:38 +00:00
Elyes HAOUAS
5ba154a597 src: Use space after 'if', 'for' 
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-05 11:37:00 +00:00
Elyes HAOUAS
6aa9d66873 src: Use space after switch, while 
Change-Id: I150591aa3624895c4c321101a251547dd23d1db5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44172
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-05 11:36:52 +00:00
Angel Pons
d1c590a666 nb/intel/x4x: Define and use HOST_BRIDGE macro 
Other Intel northbridges do this.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change

Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 22:44:06 +00:00
Angel Pons
9dfd6150bd nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs 
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:

 BIOS implementations must report these remapping structure types in
 numerical order. i.e., All remapping structures of type 0 (DRHD)
 enumerated before remapping structures of type 1 (RMRR), and so forth.

So, update the corresponding code to adhere to the specification.

Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-08-04 21:42:13 +00:00
Angel Pons
579ccdf9c9 nb/intel/x4x: Remove dead assignments 
The call to `decode_pcie_bar` always initializes these values.

Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:41:23 +00:00
Angel Pons
8f917b1d4b nb/intel/x4x: Refactor decode_pcie_bar 
Constify and eliminate local variables where possible to ease reading.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:36:32 +00:00
Angel Pons
ce3e6380b9 nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding 
Other northbridges have a `decode_pcie_bar` function. Since it's not
needed anywhere else, keep it as a static function for now.

Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:36:00 +00:00
Angel Pons
4a2f08c846 nb/intel/i945: Deduplicate PCIEXBAR decoding 
We can use `decode_pcie_bar` instead, if we make it non-static.

Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:35:26 +00:00
Angel Pons
cff4d1649f nb/intel/i945: Refactor get_pcie_bar 
Turn it into `decode_pcie_bar`, taken from gm45.

Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:35:08 +00:00
Angel Pons
1850396dc4 nb/intel/haswell: Use ASL 2.0 syntax 
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-08-04 21:33:58 +00:00
Angel Pons
302a1437cd nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax 
This brings Ironlake closer to Sandy Bridge.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43687
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-04 21:31:08 +00:00
Angel Pons
5cd8c7c3e6 nb/intel/sandybridge: Update to ASL 2.0 syntax 
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.

Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-08-04 21:30:43 +00:00
Angel Pons
ecec9474d8 nb/intel/x4x: Change signature of decode_pciebar 
Rename it and make it return an int, like other northbridges do.

Change-Id: I8bbf28350976547c83e039731d316e0911197d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:28:52 +00:00
Angel Pons
f4fa1e1d06 nb/intel/haswell: Deduplicate PCIEXBAR decoding 
Add `decode_pcie_bar` for consistency with other Intel northbridges.

Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:28:05 +00:00
Angel Pons
90de10c17a nb/intel/pineview: Refactor decode_pcie_bar 
Constify and eliminate local variables where possible to ease reading.

Tested with BUILD_TIMELESS, Foxconn D41S remains identical.

Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:27:31 +00:00
Angel Pons
653d8717ba nb/intel/pineview: Change signature of decode_pciebar 
Rename it and make it return an int, like other northbridges do.

Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:27:16 +00:00
Angel Pons
69356489fe nb/intel/pineview: Use MiB definition 
Also constify a local variable while we're at it.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 21:26:49 +00:00
Angel Pons
aaf5b09a5a nb/intel/pineview: Remove dead assignments 
The call to `decode_pciebar` always initializes these values.

Change-Id: Ide45e1e5e8b8d6cfebd2fc4e272b1971b0a9b346
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 12:23:15 +00:00
Angel Pons
c0c951630a nb/intel/gm45: Deduplicate PCIEXBAR decoding 
We can use `decode_pcie_bar` instead, if we make it non-static.

Change-Id: I4d005290355e30e6fdaae3e8e092891fddfbe4fc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-04 12:23:04 +00:00
Angel Pons
b9bbed2c41 nb/intel/gm45/northbridge.c: Use MiB definition 
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Ibfa9a6fa7818d0bd79d2c0d9331c0ca38a2b7fe3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-08-04 12:22:40 +00:00
Angel Pons
b053583a1c nb/intel/gm45: Use PCI bitwise ops 
While we are at it, also reflow a few lines that fit in 96 characters.

Tested with BUILD_TIMELESS=1, Roda RK9 does not change.

Change-Id: Icaca44280acdba099a5e13c5fd91d82c3e002bae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42189
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-08-04 12:22:04 +00:00
Keith Hui
e284bd672c nb/intel/i440bx: Make ROM area unavailable for MMIO 
Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-08-04 07:14:43 +00:00
Angel Pons
9addda3c41 nb/intel/ironlake: Add Generic Non-Core register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I4d878b5dbb5a5617143240b8f5bc5b6f5a754511
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:32:20 +00:00
Angel Pons
c642a0d894 nb/intel/ironlake: Add Generic Non-Core PCI device definition 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:32:12 +00:00
Angel Pons
a457e35237 nb/intel/ironlake: Add QPI Physical Layer registers 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I44db564c757647f493e92d35602178ef8b722517
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:59 +00:00
Angel Pons
10993c4ad4 nb/intel/ironlake: Add QPI Physical Layer device definition 
Like the QPI Link device, there can be more of these devices on
multi-socket platforms. So, name it Physical Layer 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Ia5f6e42a742bc69237de38f1833e56c8da7c4f7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:47 +00:00
Angel Pons
0814357646 nb/intel/ironlake: Add QPI Link register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Id226a2fdcbd0fe48822c4f65746e14fb00db6b2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:36 +00:00
Angel Pons
93d9517795 nb/intel/ironlake: Add definition for QPI Link PCI device 
On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:22 +00:00
Angel Pons
67573371d5 nb/intel/ironlake: Add SAD DRAM register definitions 
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:31:11 +00:00
Angel Pons
4500893062 nb/intel/ironlake: Correct PCIEXBAR definition 
This register resides within the SAD's config space, and is 64-bit.

Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:30:59 +00:00
Angel Pons
3ab19b32a2 nb/intel/ironlake: Add definition for SAD PCI device 
Let's hope this cheers up the poor System Address Decoder device.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:30:50 +00:00
Angel Pons
16fe1e0246 nb/intel/ironlake: Drop D0F0_ prefix from register names 
Only some registers have such a prefix. Drop it for consistency.

Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:57 +00:00
Angel Pons
9333b74229 nb/intel/ironlake: Rename memory map variables 
Uppercase variable names can be confused with register definitions. Use
lowercase names instead, conforming to the coding style guidelines.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I61a28bf964ea8c2c662539825ae9f2c88348bdba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:42 +00:00
Angel Pons
8bf160a9a6 nb/intel/ironlake/raminit.c: Drop unused define 
This is the only instance of `BETTER_MEMORY_MAP` in the tree.

Change-Id: I118e5b5a0f10da56e2335828477caed81c5bf855
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:30 +00:00
Angel Pons
64943a3155 nb/intel/ironlake/hostbridge_regs: Drop D0F0_PMBASE 
This register does not seem to exist on Ironlake.

Change-Id: I3fba6a3fd443f2c9eab874e1d1b8f081f58b1536
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:19 +00:00
Angel Pons
e2a2877adf nb/intel/ironlake/hostbridge_regs.h: Clean up registers 
Remove duplicated definitios and sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: Idcfa64a39c12a4ac06a342ef9b51a01b806d4c84
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:28:09 +00:00
Angel Pons
e9d1d70c7f nb/intel/ironlake: Put host bridge registers into its own file 
Looks like some registers are defined twice. Also, group some QPI
registers together. They were scattered around and mixed with the host
bridge registers, probably because other northbridges have such
registers in the host bridge's PCI config space. But not Ironlake.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I6e60f7fcb1467f302618eeab1b0d995920a98569
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:27:45 +00:00
Angel Pons
0a760cd05b nb/intel/pineview/hostbridge_regs.h: Clean up registers 
Sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2020-08-03 05:27:28 +00:00