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Author SHA1 Message Date
Martin Roth
99f967b7a5 mb/google/guybrush: Add guybrush APCBs into build 
This adds the Guybrush APCBs into the AMD firmware binary.

BUG=b:182510885
TEST=Build

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-13 02:48:16 +00:00
Nikolai Vyssotski
42cd4ddb08 soc/amd/cezanne/fsp_params.c: GOP: pass VBIOS pointer to FSP 
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver.

BUG=b:171234996

Change-Id: I504f808d85d8084e6f32f73cebf02fb0f784cd73
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-13 02:45:17 +00:00
Nikolai Vyssotski
b606953731 soc/amd/picasso/fsp_params.c: GOP: pass VBIOS pointer to FSP 
Pass PCI_VGA_RAM_IMAGE_START as VBIOS image pointer for GOP driver.

BUG=b:171234996
BRANCH=Zork

Change-Id: I49adcacf2abb914e460fbc87b488a22dca8c8af2
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-13 02:45:00 +00:00
Nikolai Vyssotski
b649d6ac11 soc/amd/common/block/graphics/graphics: GOP: load VBIOS 
Load VBIOS in pci set_resources to PCI_VGA_RAM_IMAGE_START (0xc0000)
since pci_dev_init() will not load it in GOP case (VGA_ROM_RUN is not
set). Add Cezanne GFX PID.

BUG=b:171234996
BRANCH=Zork

Change-Id: I4a6fea9b6cd60c862e15ed2ed539869c0f9bd363
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-13 02:44:40 +00:00
Mathew King
1ab35a7f50 mb/google/guybrush: Add ACPI support for Chrome EC 
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-03-13 02:37:30 +00:00
Mathew King
fc49adfe82 soc/amd/cezanne: Move globalnvs.asl to the correct location 
BUG=b:180507937
TEST=guybrush builds without globalnvs in dsdt.asl

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3ffe94f7b575126e61245bed9c9560313df2d725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51291
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-13 02:36:35 +00:00
Mathew King
d5baf6d89c mb/google/guybrush: Configure eSPI GPIOs in early stage 
BUG=b:181961514, b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-13 01:31:47 +00:00
Mathew King
d490afbe04 mb/google/guybrush: Configure early GPIOs in earliest stage 
Configure early GPIOs in verstage if it is run in PSP otherwise
configure them in bootblock.

BUG=b:181961514, b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-03-13 01:31:12 +00:00
Mathew King
7a8108deb9 mb/google/guybrush: Enable verstage 
BUG=b:181961514
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-03-13 01:30:43 +00:00
Nico Huber
a6a8df39e1 util/qemu: Add additional config file for QEMU/Q35 
The `q35-alpine.cfg` adds a lot of PCIe devices to resemble the
topology inside an Intel Alpine Ridge Thunderbolt controller.
By no means could this be detected as such a controller. But
having a real-world example of such a topology can help to
test the allocator and other algorithms on a deeper tree.

It adds two levels of PCIe switches (`alpine-root` and
`alpine-1`), and two endpoints (a `pci-testdev` and an xHCI
controller).

It can be added to the default `q35-base.cfg` config, e.g.
with:

    $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg

Change-Id: Ieab09c5b67a5aafa986e7d68a6c1a974530408b0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51329
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 23:45:14 +00:00
Nico Huber
c2ffe89f77 pci_def.h: Introduce PCI_EXP_DEVCAP2 & PCI_EXP_DEVCTL2 proper 
Replace the existing, odd looking, unordered definitions used for
LTR configuration with the usual names used by upstream libpci.

TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.

Fixes: Code looked like UEFI copy-pasta. Header file was a mess.
Change-Id: Icf666692e22730e1bdf4bcdada433b3219af568a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51327
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 23:44:57 +00:00
Nico Huber
a768deae73 device: Give pci_ops.set_L1_ss_latency a proper name 
Rename `set_L1_ss_latency` to what it does: `set_ltr_max_latencies`.

TEST=Built google/brya0 with BUILD_TIMELESS=1: no changes.

Change-Id: I7008aa18bf80d6709dce1b2d3bfbb5ea407a0574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 23:44:49 +00:00
Nikolai Vyssotski
2d24146aef soc/amd: GOP: add UPD for VBIOS buffer 
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.

BUG=b:171234996
BRANCH=Zork

Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 21:26:03 +00:00
Felix Held
7d3df29ce7 soc/amd/common/amdblocks/chip.h,psp.h: add missing stdint.h include 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6fb53d88a840a782af7502660ff85205f84523b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-12 20:32:05 +00:00
Felix Held
e77d939321 soc/amd/cezanne: add XHCI SCI/GEVENT setup 
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32fd9b7165306266613e8497b5d07473b5fea02d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-12 20:31:55 +00:00
Felix Held
8494d8a165 soc/amd/common/amdblocks/smi.h: include types.h instead of stdint.h 
gpe_configure_sci has a size_t type parameter, so we need to include
types.h instead of stdint.h here.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2879d5cf27c432871a2b9c5c90bdd539b97f9d3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-12 20:31:46 +00:00
Furquan Shaikh
f14c05f144 cpu/intel/microcode: Fix caching logic in intel_microcode_find 
CB:49896 added support in `intel_microcode_find()` to cache the found
microcode for faster subsequent accesses. This works okay when the
function succeeds in finding the microcode on BSP. However, if for any
reason, `cpu_microcode_blob.bin` does not contain a valid microcode
for the given processor, then the logic ends up attempting to find
microcode again and again every time it is called (because
`ucode_updates` is set to NULL on failed find, thus retriggering the
whole find sequence every time). This leads to a weird race condition
when multiple APs are running in parallel and executing this
function.

A snippet of the issues observed in the scenario described above:
```
...
microcode: Update skipped, already up-to-date
...
Microcode header corrupted!
...

```

1. AP reports that microcode update is being skipped since the current
version matches the version in CBFS (even though there is no matching
microcode update in CBFS).
2. AP reports microcode header is corrupted because it thinks that the
data size reported in the microcode is larger than the file read from
CBFS.

Above issues occur because each time an AP calls
`intel_microcode_find()`, it might end up seeing some intermittent
state of `ucode_updates` and taking incorrect action.

This change fixes this race condition by separating the logic for
finding microcode into an internal function `find_cbfs_microcode()`
and maintaining the caching logic in `intel_microcode_find()` using a
boolean flag `microcode_checked`.

BUG=b:182232187
TEST=Verified that `intel_microcode_find()` no longer makes repeated
attempts to find microcode from CBFS if it failed the first time.

Change-Id: I8600c830ba029e5cb9c0d7e0f1af18d87c61ad3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51371
Reviewed-by: Patrick Rudolph
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 17:33:01 +00:00
Stanley Wu
105d91e114 mb/google/dedede/var/boten: Increase Goodix touchscreen reset delay to 180 ms 
1. Follow GT7375P Programming Guide_Rev.0.6 to increase
   reset delay to 180ms.
2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin
   keep high after system suspend.

BUG=b:181711141
TEST=Build and boot boten to OS.
     Confirm TOUCH_RPT_EN pin keep low after system suspend.

Change-Id: I98efbe68dab538906802647582eba0e068d9c11f
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 17:31:06 +00:00
Stanley Wu
5c4056dd02 mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low time 
Configure I2C bus 5 high and low time for p-sensor device.

BUG=b:181727056
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-03-12 17:30:26 +00:00
Angel Pons
18edd0008c soc/intel/braswell: Factor out common acpi_fill_madt 
Function is identical for all mainboards, so factor it out.

Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 15:41:35 +00:00
Angel Pons
d37cfb7669 arch/x86/smbios_defaults.c: Default to motherboard type 
Nearly every board that coreboot supports is a motherboard.

Change-Id: I1419874a0ba3f2e21568fa4b07b88f2048d10203
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50180
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 15:36:09 +00:00
Angel Pons
122cc8c61d soc/intel/common/block/fast_spi: Clean up header 
Suffix `SPIBAR_HWSEQ_XFER_TIMEOUT` with its units, use lowercase for hex
values and rename BIOS_CONTROL macros, as the register is not in SPIBAR.

Change-Id: I3bc1f5a5ebc4c562536829e63550c0b562b67874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-03-12 11:37:51 +00:00
Michael Niewöhner
405f229689 soc/intel/*: drop UART pad configuration from common code 
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.

Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.

Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
 2021-03-12 08:48:03 +00:00
Michael Niewöhner
2b5892256c mb/intel/adlrvp: do UART pad config at board-level 
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-03-12 08:47:53 +00:00
V Sowmya
8cb7af8e7c mb/intel/shadowmountain: Enable Type-C subsystem 
This patch adds the changes to enable the TCSS.

BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 04:26:39 +00:00
Felix Held
03a4bfc54d soc/amd/common/block/smu: rename mailbox register defines 
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-12 00:48:01 +00:00
Felix Held
e995684fa1 soc/amd/common: factor out SMN access function from SMU code 
The SMU mailbox interface gets accessed over the SMN register space, so
factor out those access functions into a separate common code SMN access
building block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iabac181972c02ae641da99f47b2aa9aa28dae333
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-12 00:47:30 +00:00
Stanley Wu
5a702653cd mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm 
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch.

BUG=b:179000150
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
     un-approach：
       => register address: 0x01 value: 0x00
     approach:
       => register address: 0x01 value: 0x02
     Confirm WWAN SAR table work as expected.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-12 00:33:28 +00:00
Dmitry Torokhov
39c1b4f951 Documentation/acpi: switch example from edge to level interrupts 
Configuring touch controllers to use edge-triggered interrupts is not
recommended as it is very easy to lose an edge when kernel drivers
disable the interrupt for one reason or another, and recovering from
this condition requires workarounds in the kernel.

Unfortunately the example setting up a touchpad used edge-triggered
interrupts, and this set up has been propagating through the boards.
Let's switch the example to use level interrupts instead.

Change-Id: I4dc8b91ed070ce117553b00a087ad709aeaf16af
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-03-11 22:38:52 +00:00
Angel Pons
a70d17dba2 mb/system76/lemp9: Drop unneeded memcfg values and comments 
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory.
Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake.

Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-03-11 17:12:25 +00:00
Aamir Bohra
813a3bafa8 driver/intel/fsp2_0: Allow function to run serially on all APs 
EFI_PEI_MP_SERVICES_STARTUP_ALL_APS passes in a boolean flag singlethread
which indicates whether the work should be scheduled in a serially on all APs
or in parallel. Current implementation of this function mp_startup_all_aps
always schedules work in parallel on all APs. This implementation ensures
mp_startup_all_aps honors to run serialized request.

BUG=b:169114674

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I4d85dd2ce9115f0186790c62c8dcc75f12412e92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51085
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-11 15:54:04 +00:00
Aamir Bohra
7e0019ef20 src/cpu/x86: Add helper mp_run_on_all_aps 
Add a helper function mp_run_on_all_aps, it allows running a given
func on all APs excluding the BSP, with an added provision to run
func in serial manner per AP.

BUG=b:169114674

Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I74ee8168eb6380e346590f2575350e0a6b73856e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51271
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-11 15:53:58 +00:00
Felix Held
a5cdf75f69 soc/amd: move warm reset flag function prototypes to common code 
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-03-11 15:11:20 +00:00
Eric Lai
4626a6684c mb/google/mancomb: Add eSPI configuration 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:09:39 +00:00
Eric Lai
e6b3168ff1 mb/google/mancomb: Enable mancomb variant 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:09:29 +00:00
Eric Lai
b9204fc012 mb/google/mancomb: Enable console UART 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:09:06 +00:00
Eric Lai
c23fa81e94 mb/google/mancomb: Enable ACPI tables 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:08:51 +00:00
Eric Lai
6f06883856 mb/google/mancomb: Enable CONFIG_CHROMEOS 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:07:41 +00:00
Eric Lai
6bb5b9a058 mb/google/mancomb: Add stubs to configure GPIOs 
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
 2021-03-11 15:07:06 +00:00
Subrata Banik
0603902525 soc/intel/common/block/cpu: Use tab instead of space 
Convert the lines starts with whitespace with tab as applicable.

TEST=Built google/brya0 and ADLRVP with BUILD_TIMELESS=1: no changes.

Change-Id: Ibd11ad12caa1be866a851a8cd4bd23349e8ffbbe
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51375
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-11 05:06:43 +00:00
Jonathan Zhang
492a792d38 soc/intel/common/block: Add PCI IDs for EmmitsBurg PCH 
According to Intel EmmitsBurg EDS, doc# 606161:
* Add PCI devid for SPI.
* Add PCI devid for ESPI (LPC).

EmmitsBurg (EBG) PCH is used in the chipset with Sapphire Rapids
Scalable Processor (SPR-SP).

Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ie8925cb739c95c34febf9002149de437d19c8234
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-03-11 04:26:21 +00:00
Mathew King
238242bda4 mb/google/guybrush: Enable USB ports in devicetree 
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-11 01:17:40 +00:00
Mathew King
72cdbfa2f3 mb/amd/majolica: Enable USB ACPI in devicetree 
BUG=b:180529005
TEST=boot majolica, all USB ports work

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-11 01:17:09 +00:00
Mathew King
641690b7ae mb/google/guybrush: Enable Chrome EC SKUID and BOARDID 
BUG=b:181910592
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-03-11 01:16:20 +00:00
Mathew King
454426d9d0 mb/google/guybrush: Log mainboard events to elog 
BUG=b:180653357
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-11 01:14:32 +00:00
Mathew King
78f0301ba4 mb/google/guybrush: Add chomeec device to lpc bridge 
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-03-10 23:49:11 +00:00
Mathew King
c519bff9c1 soc/amd/cezanne: Add USB ports to chipset.cb 
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I16de0869abd1eff4e89cf1b8128775858702acb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2021-03-10 23:47:03 +00:00
Kane Chen
807ce6258a mb/google/zork/var/shuboz: support regular/numpad touchpad 
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0

BUG=b:174964012
BRANCH=zork
TEST=build pass

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
 2021-03-10 23:44:49 +00:00
Angel Pons
06b20ceb2f mb/{amd/padmelon,google/zork}: Do not select VGA_BIOS 
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.

Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-03-10 23:42:53 +00:00
Angel Pons
83f9f8983b mainboard: Drop unnecessary VGA_BIOS default 
This option defaults to n already.

Change-Id: I9f6407152f7cf2e2ac6fd1fff874e400f89a27ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-03-10 23:35:00 +00:00