Commit Graph

5121 Commits

Author SHA1 Message Date
Maximilian Brune
ee1cb8f463 mb/emulation/qemu-riscv: Change to -bios option
This changes the virt target so that it can be run with the -bios option
and a pflash backend for the flash. QEMU can now be run as follows:

qemu -M virt -m 1G -nographic -bios build/coreboot.rom \
        -drive if=pflash,file=./build/coreboot.rom,format=raw

coreboot will start in DRAM, but still have a flash to put CBFS onto and
to load subsequent stages and payload from.

Tested bootflow:
coreboot -> OpenSBI -> Linux -> u-root

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
2024-03-05 18:57:29 +00:00
Zheng Bao
92a9d93144 amdfwtool: Move the functions to handle_file.c
Change-Id: I4cfec13cbc2a86dc352758541cce915a838e0d0f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78305
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:50:53 +00:00
Zheng Bao
80b853e626 amdfwtool: Remove the function's dependency to ctx
This is for next CL to move the write_body to another source,
handle_file.c.
https://review.coreboot.org/c/coreboot/+/78305

Removing amdfwtool_cleanup in write_body will not change the
result. Write_body returns to main and amdfwtool_cleanup still ends up
getting called.

Change-Id: I639828498fa45911f430500735e90ddc198b6af5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78304
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-04 14:50:44 +00:00
Stefan Reinauer
98ecb1612c lint: Make lint work on Darwin
Darwin's getopt does not support the same parameters as the
util-linux version and so it is not possible to commit any
changes because lint fails.

Change-Id: Ife26083d2de080af9ed3d509945720051ca14bd7
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80436
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-03-02 03:55:01 +00:00
Martin Roth
10291e800c amdfwtool: Use Makefile.mk for Makefile settings
When updating the Makefiles, to keep from having to update two files at
the same time, import Makefile.mk into the external Makefile. This
allows the bulk of the settings to be in a single location.

While I'm here, I adjusted the print statements to match the rest of
coreboot.

Change-Id: Id5b869f49b34b22e6a02fc086e7b42975141a87e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-29 02:24:09 +00:00
Arthur Heymans
55b3c0466c docker/coreboot-sdk: Add meson
This is needed to build opensil. With meson and ninja added to the
coreboot-sdk image there is no need have them in the jenkins node image.

Change-Id: I36188ae895f2a770f1dc4528f332c09bf386db73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-26 17:25:00 +00:00
Martin Roth
5ff6bf30d8 util/amdfwtool: build amdfwtool only for all tools or AMD CPUs
When we're building non-AMD processors, don't bother building amdfwtool
unless we're specifically building all of the tools like for abuild.

Change-Id: I9021674a06d65a79e24020790d317ab947c505fe
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-26 14:50:18 +00:00
Elyes Haouas
04d6eb1eae crossgcc: Upgrade CMake from 3.27.7 to version 3.28.3
Change-Id: I17758e23da25d610a0b462dfd388c53b89315242
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-24 22:26:11 +00:00
Philipp Hug
1d3838b623 riscv/mb/qemu: fix qemu invocation comment
Change-Id: I773fb39801f180fead584942dfb385fcde9d2680
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80262
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
2024-02-22 22:34:57 +00:00
Felix Singer
52b51db1d9 util/crossgcc: Update LLVM from 16.0.6 to 17.0.6
Change-Id: Ifed410f4b7fdc358535f01850328c642d19ff1f6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20 10:38:23 +00:00
Elyes Haouas
824ba49a0b crossgcc: Upgrade binutils from 2.41 to 2.42
Change-Id: I6e9b2dac6fed702e8e353290971699cb9ee05dfc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-20 10:37:46 +00:00
Felix Singer
17e48e8530 util/liveiso/nixos: Install lm_sensors package
Change-Id: I6b027ed39d3ee81878e069142c2d7212f3dc0a6f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
2024-02-19 14:46:34 +00:00
Patrick Georgi
7691e96ab1 cbfstool: Support 64bit addresses for flat images
SELF has the fields wired up for 64bit, but adding flat images cuts the
upper half.

Change-Id: I3b48b8face921e942fb0e01eace791ad3e1669a0
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80576
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 21:36:08 +00:00
Maximilian Brune
732134932b util/crossgcc/buildgcc: Compile RISC-V GCC with medany
currently the HiFive Unmatched mainboard produces the following error:
```
util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/rv64imafdc/lp64d/libgcc.a
(_clzsi2.o): in function `__clzdi2':
util/crossgcc/gcc-13.2.0/libgcc/libgcc2.c:690:(.text+0x1e): relocation
truncated to fit: R_RISCV_HI20 against symbol `__clz_tab' defined in
.rodata section in util/crossgcc/xgcc/lib/gcc/riscv64-elf/13.2.0/
rv64imafdc/lp64d/libgcc.a(_clz.o)
```

This is due to the fact that the libgcc.a library is compiled with the
medlow code model but the mainboards are compiled with the medany code
model.

Changing the code model of the GCC libraries to the medany code model
fixes the issue.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: If5f07ce034686dd7fec160ea76838507c0ba7fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80139
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-18 07:53:09 +00:00
Patrick Rudolph
7d4155e6e6 util/cbfstool/linux_trampoline: Support more e820 entries
Since linux commit f9ba70535dc12d9eb57d466a2ecd749e16eca866
"[PATCH] Increase number of e820 entries hard limit from 32 to 128"
made in 2005 the number of e820 entries passed from the bootloader
is 128. Use the boot protocol version to check for support of
128 entries and use them if necessary.

Tested on IBM/SBP1:
Fixes booting a Linux payload when more than 32 entries are present
in the memory table, which can easily happen on a 4 socket platform.

Change-Id: Iec0a832fff091b6c3ae7050ef63e743a30618f25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-02-18 07:50:28 +00:00
Martin Roth
be08c1d6dc Treewide: Fix incorrect SPDX license strings
These strings didn't match the license names exactly, so update them
to match.

Change-Id: Ib946eb15ca5fa64cbd6b657350b989b4a4c1b7b7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-02-18 01:55:57 +00:00
Vojtech Vesely
21af211807 util/ifdtool.c: Fix long_options for platform
Platform has argument, but has_arg was mistakenly set to 0.

Change-Id: I7d5c31c2b1da544cb73d9e213d463332fcdba7df
Signed-off-by: Vojtech Vesely <vojtech.vesely@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80432
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
2024-02-15 09:27:21 +00:00
Felix Held
7c31352a47 util/showdevicetree: drop unmaintained tool
This tool doesn't have a makefile, when trying to compile it manually
with the given instructions it even fails to compile after fixing the
paths in the given command, and it references the non-existing
PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-14 22:07:56 +00:00
Nicholas Sudsgaard
60a68295b8 util/intelmetool: Add Intel Union Point support
The device IDs were taken from the 200 series datasheet (page 24).

Change-Id: I34b5cb61dd7b561778cc8506858cd436e6f04f9a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80419
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12 04:47:24 +00:00
Stefan Reinauer
a295ac1d44 crossgcc: Add buildgcc support for Apple M1/M2 devices
GMP and IASL don't compile with the default compiler and linker flags:
- GMP's check for the MacOS architecture hard coded x86_64 but it also
  needs to know about arm64.
- iasl does some trickery on pointer alignment to save space(?), so we
  need to tell clang about it.

Change-Id: If4cca9d3e55051a6121d992e5320bee1df17af9f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80435
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-12 04:45:03 +00:00
Patrick Georgi
3e397ddacb util/kconfig: Uprev to Linux 6.7's kconfig
Just a memory leak fix in Linux 6.7.

Change-Id: I1ff302dafa01e78429a30ff18e21ffe0b45ce46e
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80263
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-02-05 06:29:11 +00:00
Julius Werner
c228beff19 util/cbmem: Use commonlib ipchksum() algorithm
This patch switches the cbmem utility from its own IP checksum
implementation to the commonlib version (which is good because the old
one had a couple of bugs: doesn't work on odd sizes and may overflow
its carry accumulator with input larger than 64K).

Change-Id: I0bef2c85c37ddd3438b7ac6389e9daa3e4955b31
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80256
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-02-02 22:49:23 +00:00
Subrata Banik
5fe229744d util/ifdtool: Add a new switch -E to protect GPR0
This patch adds support for the new command-line option `-E` to
the ifdtool, which enables users (primarily factory users) to
protect GPR0.

Additionally, this patch refactors some code while adding support for
enabling GPR0 protection.

For more information on the scope of GPR0 (General Protection Range 0),
please refer to the Intel Meteor Lake-U Type 4 Client Platform SPI
Programming Guide, Document Number 768150.

BUG=b:270275115
TEST=Able to test GPR0 protection on google/rex and google/yahiko.

> ifdtool -p mtl -E image.bin -O image.bin_lock
...
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
...
GPR0 protection is now enabled

Change-Id: I27c533ae4109c79299f4e7ff75e750d7cc64280f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2024-02-02 05:18:32 +00:00
Arthur Heymans
7fcd4d58ec device/device.h: Rename busses for clarity
This renames bus to upstream and link_list to downstream.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-31 10:36:39 +00:00
Patrick Georgi
f67005db0a crossgcc: Distinguish bootstrap and target compiler options
GCC_OPTIONS is only used for target specific options right now,
so rename to TARGET_GCC_OPTIONS and only use them in the
non-bootstrap build.

Adapt BINUTILS_OPTIONS for consistency, even though it doesn't
have the same problem.

Change-Id: I5e4f54b758dd7daf4e69101c19dfa1212fa64cf6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80229
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-30 12:00:59 +00:00
Martin Roth
50e8579bfd util/release: Remove makefile.inc references from genrelnotes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id86ebc20cf5af5b65812c3f09235d0cba86d13f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80126
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-30 08:13:50 +00:00
Arthur Heymans
80c79a5dc3 device/device.h: Drop multiple links
Multiple links are unused throughout the tree and make the code more
confusing as an iteration over all busses is needed to get downstream
devices. This also not done consistently e.g. the allocator does not
care about multiple links on busses. A better way of dealing multiple
links below a device is to feature dummy devices with each their
respective bus.

This drops the sconfig capability to declare the same device multiple
times which was previously used to declare multiple links.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-01-29 18:23:22 +00:00
Subrata Banik
2820d2a327 util/ifdtool: Refactor GPR0 Unlock Implemetation
This patch refactors GPR0 unlock function to add few important
logic as below
1. Perform GPR0 unlock if GPR0 is locked.
2. While unlocking dump the GPRD PCH strap details
3. Additionally, print the GPR start and end range if GPR0
   protection is enabled.

TEST=Able to test GPR0 protection on google/rex and google/yahiko.

Exp 1: Trying to unlock GPR0 protection for a locked image

> ifdtool  -p mtl -g image.bin -O image.bin_unlock
File image.bin is 33554432 bytes
Value at GPRD offset (64) is 0x83220004
--------- GPR0 Protected Range --------------
Start address = 0x00004000
End address = 0x00322fff
Writing new image to image.bin_unlock

Exp 2: Trying to unlock GPR0 protection for a unlocked image

> ifdtool  -p mtl -g image.bin_unlock -O image.bin_unlock

File image.bin_unlock is 33554432 bytes
GPR0 protection is already disabled

Change-Id: Id35ebdefe83182ad7a3e735bdd2998baa0ec3ed7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80216
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2024-01-27 06:43:57 +00:00
Martin Roth
659f97c621 src, util: Clean up makefile.inc in text, help & comments
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib69236fb5d68272f92405512dc231fa75ecccaa6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26 20:15:18 +00:00
Martin Roth
20abc3517b src, util: Update toolchain.inc references to .mk
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ieaf7894f49a90f562b164924cc025e3eab5a3f7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-26 13:08:50 +00:00
Martin Roth
d0096c11b2 util/autoport: Update Makefile.inc generation to Makefile.mk
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib77cb3a0852092ac414fe0160fe10d6e58fcf660
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80127
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26 13:08:18 +00:00
Martin Roth
91aa3d88f3 util/mb: Update variant template Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2a6a4d1eb7e0d0cd32c8690caf3eff340cdb0d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80124
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26 12:43:28 +00:00
Martin Roth
1f30b244b2 util: Rename Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I434940ebb46853980596f7ad55d27a62c90280fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-01-26 12:43:18 +00:00
Martin Roth
2dd1218530 util/spd_tools: Update Makefile.inc references to Makefile.mk
Make sure that any new files generated get the Makefile.mk name.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3880d5911ff8de01751befdffc99ba5a961416f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80113
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24 11:55:25 +00:00
Martin Roth
68c73c94db */mem_parts_used.txt: Change Makefile.inc to Makefile.mk
Now that the files are renamed, make sure all references to Makefile.inc
are updated as well.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I09e235eecf0c32c80a41bfcbbd3580cce6555e10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-24 11:54:51 +00:00
Martin Roth
354389365b payloads: Rename Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie7038712de8cc646632d5e7d29550e3260bf2c62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80103
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-24 10:15:10 +00:00
Martin Roth
e3df18451c Makefiles: Rename top-level Makefiles from .inc to .mk
The .inc suffix is confusing to various tools as it's not specific to
Makefiles. This means that editors don't recognize the files, and don't
open them with highlighting and any other specific editor functionality.

This issue is also seen in the release notes generation script where
Makefiles get renamed before running cloc.

The rest of the Makefiles will be renamed in following commits.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Idaf69c6871d0bc1ee5e2e53157b8631c55eb3db9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80063
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-01-24 08:31:31 +00:00
Matt DeVillier
e9786d46fa util/superiotool: reformat alternate dump output
Reformat alternate dump output to show default values before read
values, and to use brackets to visually indicate which values differ
from the defaults.

old output:

Register dump:
idx   val    def
0x07: 0x0b   (0x00)
0x10: 0xff   (0xff)
0x11: 0xff   (0xff)
...

new output:

Register dump:
idx    def    val
0x07:  0x00  [0x0b]
0x10:  0xff   0xff
0x11:  0xff   0xff
...

TEST=build/dump registers from Erying SRMJ4 w/Nuvoton NCT6796D.

Change-Id: Idef2cc136151328b114620eb297ab8fd62b71bcd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80004
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-01-18 16:48:47 +00:00
Matt DeVillier
79b548cf3b util/superiotool: add support for Nuvoton NCT6796D
Registers and default values taken from public datasheet:
https://www.nuvoton.com/resource-files/NCT6796D_Datasheet_V0_6.pdf

TEST=build/dump SIO registers on Erying SRMJ4 mainboard

Change-Id: I0ff940a17b0c38a5ca66e90dd4e075a2b04dcfc1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18 15:15:05 +00:00
Matt DeVillier
00e9c91ff7 util/inteltool: Add support for RPL-H CPU
Add PCI IDs and descriptor strings to support the integrated
north/south bridges and GPU for the i9-13900H CPU.

---
CPU: ID 0xb06a2, Processor Type 0x0, Family 0x6, Model 0xba, Stepping 0x2
Northbridge: 8086:a706 (13th generation (Raptor Lake H family) Core Processor)
Southbridge: 8086:519d (Raptor Lake)
IGD: 8086:a7a0 (Intel(R) Iris Xe Graphics [RPL-P])
SBREG_BAR = 0xfd000000 (MEM)
---

TEST=build/run inteltool on Erying SRMJ4 mainboard, verify
PCI IDs not unknown, GPIOs dumped.

Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79962
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-18 14:59:07 +00:00
Patrick Rudolph
d323d844f7 util/autoport: Improve USB code
Currently autoport fills in USB current '0' if the detected setting
isn't one of the known settings. This works as 0 is a valid setting
from C point of view, but it's not supported on desktop PCs and on
mobile platform results in the lowest possible USB PHY gain. Thus
this might cause instabilities as the original firmware had stronger
USB drive currents and gain settings.

Add more known USB current fields to the map and generate a FIXME
as comment when the detected current isn't one of the known entries
instead of defaulting to 0.

Change-Id: I48f4d636ce3401ba188f5519b5ff45fccf13f080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78828
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-01-15 09:34:11 +00:00
Nico Huber
d7612e9765 tree: Use accessor functions for struct region fields
Always use the high-level API region_offset() and region_sz()
functions. This excludes the internal `region.c` code as well
as unit tests. FIT payload support was also skipped, as it
seems it never tried to use the API and would need a bigger
overhaul.

Change-Id: Iaae116a1ab2da3b2ea2a5ebcd0c300b238582834
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79904
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-14 02:06:11 +00:00
Elyes Haouas
336fd64de7 lint/kconfig_lint: Remove SOUTH_BRIDGE_OPTIONS
SOUTH_BRIDGE_OPTIONS Kconfig symbol is no longer used.

Change-Id: I2380f1ce48afd191755d8b3dcab0b51909f5231f
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79913
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-01-12 18:37:57 +00:00
Subrata Banik
e8cfb88d0c util/ifdtool: Enable Read Access for SPI device expansion 2 region
As per Intel Meteor Lake SPI programming doc, the BIOS region should
have a read access enabled for device expansion 2 region
(aka region 9).

This patch ensures that BIOS region is able to read the device
expansion 2 region for Intel Meteor Lake platform as known as
SPI padding region.

BUG=b:274356894
BRANCH=firmware-rex-15709.B
TEST=Able to flash screebo AP FW image using flashrom on DUT.

Without this patch:

> flashrom -p internal -r /tmp/bios.rom
flashrom 1.4.0-devel on Linux 6.1.67-09255-ge8ae3115f8b0 (x86_64)
...
...
Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific)
on internal.
Reading flash... Transaction error between offset 0x0072f000 and
0x0072f03f (= 0x0072f000 + 63)!
read_flash: failed to read (0x72f000..0x7fffff).
Read operation failed!
FAILED.
FAILED

With this patch:

> flashrom -p internal -r /tmp/bios.rom
flashrom 1.4.0-devel on Linux 6.1.68-09294-g001fdda5287d (x86_64)
...
...
Found Winbond flash chip "W25Q256JW_DTR" (32768 kB, Programmer-specific)
on internal.
Reading flash... done.
SUCCESS

Change-Id: I18c44aa9a0f890f01a889247da118b69a58936e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-01-12 06:54:23 +00:00
Ruihai Zhou
611ee33209 util/lint: Remove the extra \ in lint-stable-003-whitespace
A following error occurred when I commit, it seems that the extra `\`
after `\.md$` is unnecessary.

File Binary file src/mainboard/google/guybrush/data.apcb matches has
lines ending with whitespace.
File Binary file src/mainboard/google/skyrim/data.apcb matches has
lines ending with whitespace.
File Binary file src/mainboard/google/zork/data.apcb matches has
lines ending with whitespace.
test failed

Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79782
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2024-01-08 19:45:23 +00:00
Reka Norman
afed45dbaa util/ifdtool: Add support for extended region read/write access
Platforms from CNL onwards support up to 16 flash regions, not 12. The
permissions for regions [15:12] are stored in extended region
read/write access fields in the FLMSTR registers. Currently ifdtool
treats these fields as reserved, so they're not modified when locking or
unlocking.

Add support for extended regions so that they are locked/unlocked by the
--lock/--unlock options. This will make the locked/unlocked descriptors
generated by ifdtool match those generated by mFIT.

BUG=b:270275115
TEST=Without this change:

`ifdtool -lr -p adl` on unlocked image:
Before:
00000080  ff ff ff ff ff ff ff ff  ff ff ff ff 00 00 00 00
00000090  ff ff ff ff
After:
00000080  ff 07 20 00 ff 05 40 00  ff 00 00 00 00 00 00 00
00000090  ff 00 00 00

`ifdtool -u -p adl` on locked image:
Before:
00000080  00 07 20 00 00 05 40 00  00 00 00 00 00 00 00 00
00000090  00 00 00 00
After:
00000080  00 ff ff ff 00 ff ff ff  00 ff ff ff 00 00 00 00
00000090  00 ff ff ff

With this change:

`ifdtool -lr -p adl` on unlocked image:
Before:
00000080  ff ff ff ff ff ff ff ff  ff ff ff ff 00 00 00 00
00000090  ff ff ff ff
After:
00000080  00 07 20 00 00 05 40 00  00 00 00 00 00 00 00 00
00000090  00 00 00 00

`ifdtool -u -p adl` on locked image:
Before:
00000080  00 07 20 00 00 05 40 00  00 00 00 00 00 00 00 00
00000090  00 00 00 00
After:
00000080  ff ff ff ff ff ff ff ff  ff ff ff ff 00 00 00 00
00000090  ff ff ff ff

Change-Id: Iaa43524d91c399a996ade56f2f613b4110a44aad
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-01-08 13:05:04 +00:00
Reka Norman
c64be928de util/ifdtool: Add support for disabling GPR0
On ChromeOS devices with updateable CSE firmware, the GPR0 (Global
Protected Range) register is used to ensure the CSE RO is write
protected even when the FLMSTR-based protection is temporarily disabled
by coreboot to allow updating the CSE RW. For more details see
Documentation/soc/intel/cse_fw_update/cse_fw_update.md

Therefore to allow modifying the CSE firmware from the CPU, the
descriptor must have both the FLMSTR-based protection disabled (which
can be done using ifdtool --unlock), and GPR0 disabled.

Add an ifdtool option for disabling GPR0. For now I've added support for
all platforms for which I have the SPI programming guide. Support for
more platforms can be added in the future if needed.

BUG=b:270275115
TEST=Run `ifdtool -p adl -g image.bin -O image-unlocked.bin` on a locked
craask image, check the GPR0 field is set to 0.

Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79788
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-01-05 05:12:23 +00:00
Felix Singer
acf10d6096 util/liveiso: Update to 23.11 release
The package 'bluezFull' got superseded by 'bluez'. So just remove the
related line since 'bluez' is the default.

Change-Id: Ibf72c37205017b27012064b311a9510136351c0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-29 22:24:50 +00:00
Felix Singer
944bed2c7d util/docker/fedora: Add Dockerfile.base
Following commands were used to test if everything builds:

    * make crossgcc
    * make clang
    * make what-jenkins-does

Change-Id: I8d04c570f91215f534f173db2ae559b64b58012f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-12-29 22:14:49 +00:00
Felix Singer
68a4c2ae8d util/{cbfstool,nvramtool}: Use same indent levels for switch/case
Use same indent levels for switch/case in order to comply with the
linter.

Change-Id: I2dd0c2ccc4f4ae7af7dd815723adf757244d2005
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-20 08:35:03 +00:00