Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: LTE
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: Camera WFC
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: LTE
BUG=b:182973703
BRANCH=dedede
TEST=Build the coreboot image.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I80447d6ac3422f858a9022f550b4f42353819405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The 'device pci 00.0 on end' entries are not necessary for socketed
devices unless a chip driver needs to be bound to a device, so remove
them from the devicetree. Also remove the `drivers/wifi/generic` chip
driver as it was not necessary either.
Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The timeout is never reached when the codec is functioning properly.
Using a small timeout value can result in spurious errors with some
codecs, e.g. a codec that is slow to respond but operates correctly.
When a codec is non-operative, the timeout is only reached once per
verb table, thus the impact on booting time is relatively small. So,
use a reasonably long enough timeout to cover all possible cases.
Remove the unconditional 25 µs delay and increase the timeout delay.
The new value of 1 ms is the maximum of all existing implementations.
Currently, the only boards using this code are AMD reference boards:
- AMD Bilby
- AMD Mandolin
- AMD Padmelon
Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested with TianoCore payload (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10
Not working:
- Discrete/Hybrid graphics
This requires a new driver to work correctly, which will be added and
enabled later.
Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.
This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.
Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.
With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none
Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache
(CB:51620). To have more compact space usage, reduce BOOTBLOCK size from
64K to 60K (only 44K needed), and move starting address of DRAM blob
(DRAM_INIT_CODE) to 0x210000 (64K-aligned).
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=asurada
Cq-Depend: chrome-internal:3704751
Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h
BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and
there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit
the array lengths accordingly to cause build errors on invalid configs.
Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorganize romstage.c to resemble sandybridge, and move everything that
needs `pei_data` into raminit.c function `perform_raminit`. Barring USB
settings, coreboot code no longer depends on pei_data.h definitions. It
still depends on MRC, though. For now.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
eDP panel flicker during system idle state is observed.
Disabling USB2 SUS well power gating can remove flicker symptom.
Please refer to doc#634894 for more details.
BUG=b:182323059
BRANCH=None
TEST=Boot and confirm no display flicker.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE.
Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H4AAG165WB-BCWE DDR4 memory parts.
BUG=b:181732562
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the cret variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:181325655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CRET
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When the soc_get_mbox_address functions returns 0 after not being able
to find an initialized PSP base address MSR or in case of Stoneyridge
the PSP's BAR3, the code will print an error string. This string needs
to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one,
since in Picasso and Cezanne only the former one is present.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Lynx Point reference code version 1.9.1 and soc/intel/common/hda_verb.c
perform these steps. Add them to Lynx Point as well. With this change,
Lynx Point and soc/intel/common hda_verb.c files are now identical.
Change-Id: I2fc592f73697a43bd5a3315ac80c77ff9f00da9b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch is trying to address some of the concerns raised in CB:50247
after the patch had landed. The preference for alphabetized headers was
just supposed to discourage leaving headers completely unordered, and
wasn't intended to disallow other intentional include orderings such as
grouping local includes after system ones or specific ordering
constraints that exist for technical reasons. This patch adds a few more
sentences to try to clarify that.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6825f4a57613fabb88a00ae46679b4774ef7110b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.
Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.
Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.
Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use timer.h helpers instead of open-coding timeout handling in polling
loops. The 25-microsecond delay in `wait_for_valid` looks odd, and may
be removed in subsequent commits. For now, preserve existing behavior.
Change-Id: Id1227c6812618597c37408a7bf53bcbcae97374a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50789
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
