4b3dbbaa4b
mb/aopen/dxplplusu: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I3f9b31a2bfb85ceb9ff833c076e062291c944923
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:48:14 +00:00
7e9654aa71
mb/intel/glkrvp: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:47:42 +00:00
ea1953f492
nb/intel/ironlake/raminit.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:47:13 +00:00
cdee5e9d12
sb/intel/lynxpoint/me_9.x.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I88cb6116c112b76336846d01e31f2cd40d6ca4cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:46:49 +00:00
3c05531632
sb/intel/i82801gx/azalia.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I0fbdf8d7a3d89fefcd321dc3ba4ddd82c309e667
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:46:15 +00:00
2047588de5
sb/ti/pci7420: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I51a2b71abc7762b550f69f2980dd34f0e4947ab5
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43219
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 23:45:38 +00:00
f29e0ea2a0
drivers/pc80/pc/i8259c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:45:08 +00:00
8dc5f3017d
device/pci_device.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Id3f9dd264e82f93a438422e388d70e3f88ae0df9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:44:44 +00:00
dc4a8d0260
cpu/intel/model_2065x/model_2065x_init.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I16fe12368ce7ffe2fd4d2a5580dd92c19a695848
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:44:04 +00:00
8a13206549
cpu/intel/model_206ax/finalize.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I76bf20bb2ec1cdd7ffee4430c80609978afaa1a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
2020-07-09 23:43:30 +00:00
5eb75fe550
vc/amd/fsp/picasso: add comment on logical lane numbers in descriptor
...
The expected lane numbers in the fsp_pcie_descriptor struct are the
logical and not the physical ones.
Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43311
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 23:20:04 +00:00
357cc6552a
include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definition
...
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.
Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.
TEST=Checked the code and the corresponding BKDG/PPR.
Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 23:19:31 +00:00
66dcda9e15
util/inteltool: add PCI ID for ICH10DO
...
Change-Id: I3561679ef50f4c094d2503539074c957f759ecef
Signed-off-by: Idwer Vollering <vidwer@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:54:33 +00:00
7c3192e44b
arch/arm/include/smp/spinlock.h: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43255
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:37:17 +00:00
c4b6a8a4d7
soc/samsung/exynos5420: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I4f06e5e8a0d25308ba56d09a3d8b71f04dbd27b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org >
2020-07-09 21:37:01 +00:00
6dd466c002
soc/intel/broadwell/pcie.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ia314148abc900685d85aede3add480614fa8e99c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Michael Niewöhner
2020-07-09 21:29:37 +00:00
20d7bd0291
security/vboot/secdata_tpm.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ie01d65f80caf32a8318d5109ad48321661c5a87b
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43213
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:29:27 +00:00
649fc6bb8a
security/tpm/tss/tcg-1.2/tss.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ifda2bbd87cd8ef5ec8e449d2c4d303be37b4d7c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43212
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:29:16 +00:00
5532d93990
soc/samsung/exynos5250: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I4772680875b20308e57da073bbcdc4597aeed893
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:28:25 +00:00
4a1938f186
sb/intel/bd82x6x/pcie.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43216
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:22:17 +00:00
bab37a2a2d
sb/intel/i82801gx/pcie.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43218
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:21:27 +00:00
0a65b738d5
sb/intel/lynxpoint/pcie.c: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 21:20:53 +00:00
5ac928dd14
soc/amd/picasso: Always load and run display oprom
...
The kernel requires the display oprom is loaded and ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:160560510
TEST=Boot Trembyle in developer mode and normal mode
Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf
Signed-off-by: Rob Barnes <robbarnes@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2020-07-09 19:34:09 +00:00
649505b077
mb/asrock/b85m_pro4: Add Super I/O GPIO table
...
Information taken from the boardviews. We are not configuring any GPIO
in bootblock, but we may want to do so in the future.
Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 18:14:02 +00:00
822b267a8c
mb/asrock/b85m_pro4: Properly select muxed functions
...
The old values were completely out of whack. Use the same settings as
vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites
configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2020-07-09 18:13:45 +00:00
03f0e43a3c
haswell: Drop GPIO indirection layers
...
This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
2020-07-09 16:25:43 +00:00
f0b5e91b1b
mb/google/slippy: Put GPIOs in a C file
...
This will allow dropping the pointer inside romstage_params.
Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
2020-07-09 16:25:18 +00:00
91aae2e0bc
mb/google/beltino: Put GPIOs in a C file
...
This will allow dropping the pointer inside romstage_params.
Change-Id: I536225351a0353298381c16cff25f39098c19bba
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
2020-07-09 16:25:08 +00:00
9b29e5e1a0
sb/intel/lynxpoint: Drop RCBA reg script mechanism
...
It is no longer used anywhere. Drop it before it rots.
Change-Id: I4bc3d5bd898058e575144a3c6c3fccb78dcff2e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
2020-07-09 16:24:37 +00:00
6e1c471f70
haswell: Turn RCBA configuration into a function
...
Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-07-09 16:23:16 +00:00
2cb3cc5238
mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driver
...
The common fast SPI driver has a function to set up the SPI OPCODE menu.
Use this function here instead of coding it again as it results in the
very same register values being written.
TEST=Compare register values in both cases and make sure they match.
Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda
Signed-off-by: Werner Zeh <werner.zeh@siemens.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43166
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: <uwe.poeche@siemens.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 14:03:07 +00:00
93084103d9
mb/lenovo/t440p/romstage.c: Drop empty function
...
There's a weak definition in chipset code that does nothing as well.
Change-Id: I2531e8b9d48eb4a1a667f22a81bb082ec98c1199
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi >
2020-07-09 13:46:40 +00:00
a5c970d433
soc/intel/baytrail/pmutil.c: Constify string arrays
...
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com >
2020-07-09 13:37:33 +00:00
61dee5c865
soc/intel/baytrail/pmutil.c: Do not hardcode num_bits
...
This can result in accesses outside array bounds. Copy what Braswell
does, which is slightly safer.
Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com >
2020-07-09 13:37:23 +00:00
26b49cc9a3
soc/intel/baytrail: Align whitespace and comments
...
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-07-09 12:47:47 +00:00
b5320b2dc1
soc/intel/baytrail: Rename "pmc.h" to "pm.h"
...
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-07-09 12:46:35 +00:00
8104effa0d
mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
...
Refer to commit 7736bfcsubrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 12:44:26 +00:00
96dec04207
soc/intel/braswell: Drop some BIOS_SPEW printk's
...
This reduces the differences between Bay Trail and Braswell.
Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2020-07-09 12:44:04 +00:00
f7c551cf6e
soc/intel/braswell/lpss.c: Use 16-bit ops on PCI COMMAND
...
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.
Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com >
2020-07-09 12:42:40 +00:00
7f87812c30
libpayload: cbgfx: Replace bilinear resampling with Lanczos
...
This patch improves the image resampling (scaling) code in CBGFX to use
the Lanczos algorithm that is widely considered the "best" resampling
algorithm (e.g. also the first choice in Python's PIL library). It is of
course much more elaborate and therefore slower than bilinear
resampling, but a lot of the difference can be made up with
optimizations, and the resulting code was found to still produce
acceptable speeds for existing Chrome OS UI use cases (on an Arm
Cortex-A55 device, time to scale an image to 1101x593 went from ~88ms to
~275ms, a little over 3x slowdown). Nevertheless, if this should be too
slow for anyone there's also an option to tune it down a little, but
still much better than bilinear (same operation was ~170ms with this).
Example images (scaled up by a factor of 7):
Old (bilinear): https://i.imgur.com/ytr2n4Z.png
New (Lanczos a=3): https://i.imgur.com/f0vKluM.png
Signed-off-by: Julius Werner <jwerner@chromium.org >
Change-Id: Idde6f61865bfac2801ee4fff40ac64e4ebddff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
2020-07-09 00:32:17 +00:00
96b00a50f1
libpayload: Add simple 32.32 fixed-point math API
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struct fraction is slooooooooooow. This patch adds a simple 64-bit
(32-bits integral, 32-bits fractional) fixed-point math API that is
*much* faster (observed roughly 5x speed-up) when doing intensive
graphics operations. It is optimized for speed over accuracy so some
operations may lose a bit more precision than expected, but overall it's
still plenty of bits for most use cases.
Also includes support for basic trigonometric functions with a small
lookup table.
Signed-off-by: Julius Werner <jwerner@chromium.org >
Change-Id: Id0f9c23980e36ce0ac0b7c5cd0bc66153bca1fd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
2020-07-09 00:32:11 +00:00
56b2550316
soc/amd/picasso: Remove I2C4
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Remove I2C4 since it is a slave device used for USB-C mux control
and should not be included with the other master devices.
BUG=b:160624619 b:160292546
TEST=EC can communicate with AP mux I2C4 slave
Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d
Signed-off-by: Edward Hill <ecgh@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 00:27:52 +00:00
037ee4b556
soc/amd/picasso: Add dummy spinlock for psp_verstage
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If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org >
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-09 00:26:05 +00:00
85dcd2f1ea
mb/google/zork: Do not select VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for Vilboz
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This change drops the selection of VARIANT_SUPPORTS_PRE_V3_SCHEMATICS
for Vilboz since it did not have any build with pre-v3 schematics.
Change-Id: I3919ad43e1dae95a4fa71073e83865e92f30dfec
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43225
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 23:07:50 +00:00
30ee0d881b
mb/google/zork: Add helpers for v3 schematics and wifi power enable
...
This change adds following two helper functions:
1. variant_uses_v3_schematics() - Check whether the variant is using
v3 version of schematics.
2. variant_has_active_low_wifi_power() - Check whether the variant is
using active low power enable for WiFi.
In addition to this, Kconfig options are reorganized to add two new
configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and
VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper
functions to return `true` early without checking for board version.
Eventually, when a variant decides to drop support for pre-v3
schematics, it can be dropped from selecting
VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant
decides to drop support for active high power enable for WiFi, it can
be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH.
Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 23:07:34 +00:00
ca36acf773
mb/google/zork: Move GPIO_137 configuration to ramstage
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This change moves the configuration of GPIO_137 to happen in ramstage
since there is nothing in coreboot that requires the state of write
protect GPIO for zork.
Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 23:07:27 +00:00
e6b415f0e3
mb/google/zork: Do not share "write protect" information with depthcharge
...
This change removes "write protect" entry from the list of GPIOs
shared with depthcharge as done for other Chrome OS boards in CB:39318.
Change-Id: Ibd39e8d6835e465b2ab5eebcc245e45db5d84deb
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43222
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 23:07:20 +00:00
715b9555de
mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeup
...
This results in a wake from S5 as well. Since the PS/2 keyboard now
works, this behavior is annoying and, therefore, undesired.
Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42431
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 22:51:01 +00:00
934f683078
mb/asrock/b85m_pro4: Correct GP01 output level
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This allows the CPU fan tach signal to reach the Super I/O.
Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 22:45:47 +00:00
09b9b1673f
mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetree
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Otherwise, there are complaints about it from the allocator.
Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-07-08 22:45:35 +00:00
