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d624e74f7b91198f06ab1cebf586be2a094c7d35
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10 Commits

Author SHA1 Message Date
Subrata Banik
d624e74f7b soc/intel/meteorlake: Update IFD_CHIPSET kconfig value 
This patch updates IFD_CHIPSET kconfig value from `ifd2` to `mtl`.

TEST=Able to build and boot Google/Rex image on MTL emulation
platform.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416f881bcbe3dd7494ead636d6b593366a51b31c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-07 13:07:13 +00:00
Subrata Banik
e0ddbbb0d2 soc/intel/meteorlake: Enable X2APIC 
This patch enables X2APIC to avoid hang-ups due to
`Switching from X2APIC to XAPIC mode is not implemented.` 

BUG=b:237924211 ([MTL-FSP][v2222.1] Lists of boot issue with MTL FSP)
TEST=Able to enable X2APIC on rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I58649a9a6c9c0ba86856f6aa5fb470e2ef774e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65617
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2022-07-05 13:07:29 +00:00
Subrata Banik
e88bee7219 soc/intel/meteorlake: Use coreboot native event handler for FSP-M/S 
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.

BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:

Before:

Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

With this code change:

[SPEW ]  Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ]  Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ]  Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ]  The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ]  Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ]  Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ]  Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-07-03 04:57:58 +00:00
Ravi Sarawadi
e02fd83eba soc/intel/mtl/acpi: Add SoC ACPI directory for Meteor Lake 
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-29 05:29:00 +00:00
Ravi Sarawadi
91ffac8c04 soc/intel/mtl: Do initial Meteor Lake SoC commit till ramstage 
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API

BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-29 05:28:39 +00:00
Subrata Banik
febd3d756b soc/intel/meteorlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiB 
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time (~30ms).

Backport changes from commit hash 84532dae1 (soc/intel/alderlake:
Change VBOOT_HASH_BLOCK_SIZE to 4 KiB).

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-29 05:28:15 +00:00
Ravi Sarawadi
8069b5d3f2 soc/intel/mtl: Do initial Meteor Lake SoC commit till romstage 
List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API

BUG=b:224325352
TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-06-29 05:27:52 +00:00
Angel Pons
054ff5e923 soc/intel/*/Kconfig: Fix typo in comment 
clcok ---> clock

Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
 2022-06-27 13:47:55 +00:00
Subrata Banik
ea4f8c28fd soc/intel/meteorlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KB 
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix
cbmem buffer overflow issue.

Test=Boot MTL simics and check cbmem -c | grep 'CBFS: Found'
lists all stages.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5dc5d5b99003b59b2262bd1e4eb5ccb11d721195
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-06-06 17:52:03 +00:00
Ravi Sarawadi
b8224f48fe soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock 
Base code is based of Intel Alder Lake SOC code.

List of changes:

1. Add required Meteor Lake SoC programming till bootblock
2. Include only required headers into include/soc
3. Include MTL-P related DID, BDF
4. Ref: Processor EDS documents
	vol1 #621483, vol2 #640858

TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-06-06 17:51:31 +00:00