Tim Wawrzynczak
d6ac209c74
mb/google/brya/acpi: Remove erroneous _PR0/_PR3
...
The Linux kernel runtime D3 framework expects a PCIe device to have a
power resource in order to be properly power-manageable. The _PR0/_PR3
values were pointing at the PEG0 Device, which is not a PowerResource,
so this must have confused the RTD3 framework and RTD3 was not
functional. Removing the _PR0/_PR3 fixes the problem.
BUG=b:243888246
TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control;
sleep 10;
echo on > /sys/bus/pci/devices/0000:01:00.0/power/control
After this there are no longer errors seen in dmesg about failing
to place the device into D0.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Cliff Huang <cliff.huang@intel.com >
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-09-12 12:31:12 +00:00
Tim Wawrzynczak
63aca9233b
mb/google/brya/acpi/power: Clean up ASL code
...
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few
minor cleanups, but nothing functional.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Tarun Tuli <taruntuli@google.com >
2022-09-12 12:25:07 +00:00
Tim Wawrzynczak
7bc8fd58a3
mb/google/brya/acpi: Save/restore/clear some registers over GCOFF
...
Similar to the prior CL (commit db8ad5e), do the same register dance
before/after GCOFF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com >
Reviewed-by: Cliff Huang <cliff.huang@intel.com >
Reviewed-by: Tarun Tuli <taruntuli@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-09-12 12:24:51 +00:00
Tim Wawrzynczak
4dfcd7acdc
mb/google/brya/acpi: Save/restore/clear some registers over GC6
...
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config
space for the PCIe root port before/after GC6 entry. Also the detectable
error bit should be cleared, as there may be errors expected during the
GC6 flow.
BUG=b:214581763
TEST=no more correctable errors after GC6 entry/exit
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
2022-09-01 14:08:46 +00:00
Tim Wawrzynczak
e0ddb37ae8
mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methods
...
This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).
TEST=GC6 and GCOFF sequences still work
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-08-18 18:28:04 +00:00
Tim Wawrzynczak
bcc3059d83
mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIO
...
For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
2022-08-18 18:28:04 +00:00
Tim Wawrzynczak
74633b5580
mb/google/brya/acpi: Add minimum off timer for GCOFF
...
By moving the large wait for FBVDD discharge from PGOF
to PGON, the whole time may be avoided if enough time has
elapsed between the successive calls.
BUG=b:239719056
TEST=With Nvidia test software, verify ACPI prints
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I891aa14f120d58c45b8965038a9d2f2a417b3f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Cliff Huang <cliff.huang@intel.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-08-16 14:20:25 +00:00
Tim Wawrzynczak
57acfad0bc
mb/google/brya/acpi: Fix GC6 entry and exit sequences
...
Now that the virtual wire situation is figured out, the GC6 sequence
is updated to match the latest HW design guide from Nvidia. This
allows Nvidia test software to (mostly) successfully execute the GC6
test, but with some PCIe AER errors.
BUG=b:214581763
TEST=tested with Nvidia test software
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ia094c4fa9b4db094a59b9b6f02be1a649ee8569b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-08-16 14:20:18 +00:00
Tim Wawrzynczak
66d090b664
mb/google/brya/acpi: Fix PERST# handling in GC6 exit
...
PERST# is supposed to be de-asserted in GC6 exit, but the original
patch used the CTXS Method, which drives a GPIO low, instead of
STXS, because PERST# is active-low. This patch fixes that.
BUG=b:214581763
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ib0adb8efe5e2cc733ae2228614c58c124ba3f11b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
2022-08-07 19:34:23 +00:00
Tim Wawrzynczak
5625dace84
mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFF
...
When the dGPU is entering GCOFF, the link should first be placed into
L2/L3 as appropriate for the design, then when exiting, the link should
be placed back into L0. This patch fixes that oversight.
BUG=b:239719056
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-07-28 20:02:56 +00:00
Tim Wawrzynczak
17d71937a1
mb/google/brya/var/agah: Optimize dGPU GCOFF entry
...
After staring at lots of scope shots, the EE has determined that a few
modifications to the GCOFF sequence can be made:
- Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion
- Remove delay after ramping down FBVDD
This patch implements these minor changes.
BUG=b:240199017
TEST=verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-07-28 20:02:42 +00:00
Tim Wawrzynczak
bebdd4fb8a
mb/google/brya/acpi: Fix GPIO assignment for GPIO_GPU_NVVDD_EN
...
GPIO_GPU_NVVDD_EN is incorrectly (duplicately) assigned to GPP_A19 in
power.asl, but a double check of the schematic shows that the actual pad
is GPP_A17, so this patch fixes that.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I4432b50c737508b7e0d595423d614a723d2499c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-13 16:11:02 +00:00
Tim Wawrzynczak
21b187872e
mb/google/brya/acpi: Remove NV_33 power rail from GC6 entry/exit sequences
...
I misread my notes when writing the code for the GC6I/GC6O Methods, and
accidentally included NV_33 in the GC6 sequence, which is incorrect
(confirmed in the Hardware Design Guide). This patch removes the code
that brings NV_33 up and down during the GC6 sequences.
BUG=b:236676400
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Iaa6c5ef3d7b1edbe13257f99013ab0e4382bdbf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65565
Reviewed-by: Robert Zieba <robertzieba@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-13 16:10:36 +00:00
Tim Wawrzynczak
ce29eab035
mb/google/brya/acpi: Keep track of dGPU power state
...
To avoid extraneous calls from the kernel to _ON or _OFF, keep track
of the power state of the GPU in an integer and exit _ON and _OFF
routines early when attempting to enter the current state.
BUG=b:236676400
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ie874fcdc7022c4fde6f557d1ee06e8392ae3d850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Robert Zieba <robertzieba@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-07-13 16:08:37 +00:00
Tim Wawrzynczak
e88989a5d4
mb/google/brya/var/agah: Update FBVDD power-down delay
...
The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-07-07 13:48:07 +00:00
Tim Wawrzynczak
6e25ab79cd
mb/google/brya/{var/agah,acpi}: Update GPU GCOFF sequence for power down
...
We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Robert Zieba <robertzieba@google.com >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-06-24 21:54:37 +00:00
Tim Wawrzynczak
9803964301
mb/google/brya/var/agah: Fix ACPI power sequencing
...
Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
2022-06-08 12:50:48 +00:00
Tim Wawrzynczak
c852533379
mb/google/brya: Add PEG and initial Nvidia dGPU ASL support
...
Some brya variants will use a GN20 series Nvidia GPU, which requires
quite a bit of ACPI support code to be written for it. This patch
lands a decent bit of the initial code for it on the brya platform,
including:
1) PEG RTD3 methods
2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods)
3) NVOP _DSM method
There will be more support to come later, this is all written to
specifications from the Nvidia Software Design Guide for GN20.
BUG=b:214581763
TEST=build patch train
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Subrata Banik <subratabanik@google.com >
2022-05-20 14:58:46 +00:00
