The bugs happen on real hardware or in qemu with KVM enabled.
The very same code runs on some real devices and it runs in qemu
with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Do not mislead newcomers into thinking the GM45 series laptops are hard
to flash. Describe the simple coreboot flashing procedure first, then
explain how to remove the ME firmware and use a custom flash layout.
Also, reword a sentence on the simple flashing procedure for clarity.
Change-Id: Ie83ec3d20f00e9d9c869e483e24d601506857f07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com>
Reviewed-by: Evgeny Zinoviev <me@ch1p.io>
This change adds details memory mapped window handling in cbfstool
required for x86 platforms. It also captures the details about the
newly added support for multiple decode windows.
BUG=b:171534504
Change-Id: Icf970f951e56d717e6a4f8845fc73f10d5a21dd0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
- Drop vanished issue on PCIe warning
- Drop TODO section, since the TODOs are done
- Document the jumper J6, that was not documented by the vendor. Its
function has been determined by dissecting a dead board.
- The flash is not socketed anymore. Drop that note and compress the
whole paragraph. Also add a note about flashing via the BMC web
interface.
Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The code is based on autoport, with necessary modifications.
This laptop uses SMSC MEC1322 embedded controller, but the EC
interface is the same as the EliteBook laptops of previous generations
that use KBC1126 EC. So it still uses ec/hp/kbc1126, but does not need
EC firmware inserted into CBFS. We also need to leave the end of the
OEM flash content untouched, so the default ROM size is set to 12MiB
instead of 16MiB, and we need to modify the IFD when flashing.
Thanks to persmule for providing the laptop and pointing out how to
program the system flash chip of it.
Change-Id: I2328c43cbb1f488aa1d0ddd9116814d971e5d8ae
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We all knew this was coming, 32 bits is never enough. Doing this early
so that it doesn't affect too much code yet. Take care of every usage of
fw_config throughout the codebase so the conversion is all done at once.
BUG=b:169668368
TEST=Hacked up this code to OR 0x1_000_0000 with CBI-sourced FW_CONFIG
and verify the console print contained that bit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6f2065d347eafa0ef7b346caeabdc3b626402092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45939
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SMMSTORE version 2 is a complete redesign of the current driver. It is
not backwards-compatible with version 1, and only one version can be
used at a time.
Key features:
* Uses a fixed communication buffer instead of writing to arbitrary
memory addresses provided by untrusted ring0 code.
* Gives the caller full control over the used data format.
* Splits the store into smaller chunks to allow fault tolerant updates.
* Doesn't provide feedback about the actual read/written bytes, just
returns error or success in registers.
* Returns an error if the requested operation would overflow the
communication buffer.
Separate the SMMSTORE into 64 KiB blocks that can individually be
read/written/erased. To be used by payloads that implement a
FaultTolerant Variable store like TianoCore.
The implementation has been tested against EDK2 master.
An example EDK2 implementation can be found here:
eb1127744a
Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The USB4 retimer device needs to declare a _DSM with specific functions
that allow for GPIO control to turn off the power when an external
device is not connected. This driver allows the mainboard to provide
the GPIO that is connected to the power control.
BUG=b:156957424
Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To get the HDA verbs from the OEM firmware, open the firmware with
UEFITool, search for the existing HDA verbs, extract the UEFI module
and look for the verbs. Copy the consecutive 4 dword sets that look
like HDA verbs.
It is tested to make audio output from both the speaker and headphone
work.
Change-Id: Ie359fdf6785b1c0be8dc201cd76176c0a7fe7942
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When the declaration is done after the default, menuconfig will see that
symbol defined at the first place where kconfig tool will find it.
For example, if we run menuconfig and search for 'MAINBOARD_VENDOR', we
will see it defined at ""src/mainboard/51nb/Kconfig" which is odd.
Change-Id: I215a1817e60e6deb6931679f139d110ba762d3c8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes
Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM
Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
* Add a helper function to jump to arbitrary code in protected mode,
similar to the real mode call handler.
* Doesn't affect existing x86_32 code.
* Add a macro to cast pointer to uint32_t that dies if it would overflow
on conversion
Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.
TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.
Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
