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3115 Commits

Author SHA1 Message Date
Elyes HAOUAS
fcdb03358d acpi: Drop wrong _ADR objects for PCI host bridges 
Found-by: ACPICA 20191018
Change-Id: I81286d89da933b503f605737f28772bfb08483a3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36253
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-24 09:28:28 +00:00
Elyes HAOUAS
bec78e32d6 src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>' 
Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-10-21 14:21:09 +00:00
Arthur Heymans
f240a3269e nb/intel/nehalem/vboot: Ignore invalid POSTINIT on TPM startup 
During the raminit the CPU gets reset but the platform does not. To
deal with TPM init failure (a TPM can only be started up once) ignore
the invalid POSTINIT return code.

Change-Id: Ib15e796914d3e6d5f01b35fa46b3ead40f56122b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36055
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-17 15:07:57 +00:00
Arthur Heymans
7689a0f792 nb/intel/nehalem: Only enable_smbus once 
This is already done in nb/intel/nehalem/romstage.c.

Change-Id: I2dc34af874ac96af31ca9ebe6a43b2805da32d18
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-10-17 15:02:46 +00:00
Arthur Heymans
2878c0b6dc nb/intel/nehalem: use pmclib to detect S3 resume 
During the raminit the CPU gets reset, so reprogram those bits in
PM1_CNT such that the CPU remains aware that this is a S3 resume path
after the reset.

Change-Id: I8f5cafa235c8ab0d0a59fbeeee3465ebca4cc5d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-10-17 15:02:28 +00:00
Arthur Heymans
b572c9d5e5 nb/intel/nehalem: Add some debug output 
Change-Id: Icbdada0a8cdbcface5124a5f9ebd3d667c376902
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-17 15:01:38 +00:00
Arthur Heymans
c892db6398 nb/intel/nehalem: Change the output verbosity of raminit timings 
This decreases the output verbosity of RAM_DEBUG to be useful.

Change-Id: I9fa681303da0e063dd2ca789d7711151b2365f16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-17 15:01:11 +00:00
Arthur Heymans
29e53582cc nb/intel/gm45: Don't run graphics init on s3 resume 
This assumes ACPI aware OS also have a driver for this particular
hardware, which is the case for at least Linux. This saves ~60ms on S3
resume.

Change-Id: I2dcd399fee8e2d1cd1b70e60e1669a49c7aa8cb4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-14 08:16:00 +00:00
Arthur Heymans
9ed0df4c38 sb/intel/i82801ix: Add common code to set up LPC IO decode ranges 
This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-14 08:15:49 +00:00
Arthur Heymans
2ea4efeefa nb/intel/nehalem: Start VBOOT in bootblock with a separate verstage 
Tested on Lenovo Thinkpad X201, selects slot or recovery just fine.

Change-Id: Ia2b2f2b95510388599266264eaed0d64ce9b6ec5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-13 12:46:32 +00:00
Arthur Heymans
2882253237 nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK 
A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
  against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
  existing bootblock_mainboard_early_init().

Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-13 12:46:18 +00:00
Arthur Heymans
b9c9cd75e7 sb/intel/ibexpeak: Move some early PCH init after console init 
Some of the initialization isn't necessary before console INIT is
done.

EHCI debug still works fine on the Lenovo Thinkpad X201.

Change-Id: I0c33efd98844f7188e0258cf9f90049d45145e7c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35949
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-13 11:07:00 +00:00
Arthur Heymans
2437fe9dfa sb/intel/i82801gx: Move CIR init to a common place 
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.

Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-10-11 12:21:25 +00:00
Arthur Heymans
246334390b nb/intel/pineview/Kconfig: Remove romcc leftover 
This is unused since C_ENVIRONMENT_BOOTBLOCK is used.

Change-Id: Id5af41e455d211eba89cfeb625f4c728b4145da7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-10 15:38:45 +00:00
Nico Huber
51b75ae50a device: Use scan_static_bus() over scan_lpc_bus() 
Devices behind LPC can expose more buses (e.g. I2C on a super-i/o).
So we should scan buses on LPC devices, too.

Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-08 12:59:56 +00:00
Arthur Heymans
c73c92368f sb/intel/nm10: Fix enabling HPET 
RCBA_HPTC needs to be read back to consistently enable HPET.
This ought to fix raminit failing sometimes and SeaBIOS endlessly
waiting for user input.

TESTED on Intel D510MO, Fixes SeaBIOS waiting for input, without a
timeout.

Change-Id: I20a25fd97cd09fedb70469262c64d8d3828bb684
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35758
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-06 22:11:32 +00:00
Arthur Heymans
38750f88fc nb/intel/nehalem: Don't run graphic init on S3 resume 
The assumption is made that an ACPI aware an OS does not rely on
firmware to initialize the display.

TESTED on a Lenovo Thinkpad X201 with Linux 5.2, display still works
after S3, more than 200ms in time saved (dropped from 411ms to 182ms
in total in one test).

Change-Id: I36219e6d04db561d4f2ddb6e962166c598d5bc4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-10-06 10:15:30 +00:00
Arthur Heymans
3b452e0a79 nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak 
This change does the following:
- Move PCH init code from the common romstage to sb code, this allows
  for easier reuse in bootblock
- Provide a common minimal LPC io decode setup, mainboards can
  override this in the mainboard_lpc_init if required
- Set up LPC generic IO decode up in romstage based on devicetree
  settings
- Remove the ramstage LPC generic IO decode from ramstage as this is
  now done in romstage.c
- Get rid of unneeded setup of spi_read configuration in BIOS_CNTL as
  this is already done in the bootblock.

Change-Id: I3f448ad1fdc445c4c1fedbc8497e1025af111412
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-10-06 10:15:16 +00:00
Arthur Heymans
cea4fd9bb0 nb/intel/nehalem: Move romstage boilerplate to a common location 
Move the mainboard_romstage_entry to a common location and provide
mainboard specific callbacks.

Change-Id: Ia827053617cead5d2cf8e9f06cb68c2cbb668ca9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-10-06 10:15:05 +00:00
Arthur Heymans
896a2430d8 nb/intel/nehalem: Don't link walkcbfs.S in romstage 
Change-Id: I5bb0c38353d340cc5d356fba299a4460e3f5bddc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35770
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-06 10:14:53 +00:00
Arthur Heymans
f266dc6174 nb/intel/nehalem: Remove bogus GT PM init 
This was simply copied from sandybridge/gma.c.
All these registers read back 0xffffffff or 0 or don't respond to
reads.

Change-Id: I094e7caa889a3175477aa78b91545ca804d423c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35746
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-06 10:13:05 +00:00
Arthur Heymans
28bca0546b nb/intel/nehalem: Disable PEG and IGD based on devicetree 
Tested on Thinkpad X201: PEG device hidden.

Change-Id: Ib378458a55e18cc02fc49b3e6d6939d31dd4aa65
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35744
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-06 10:12:53 +00:00
Arthur Heymans
6d13a0a78a nb/nehalem: Remove bogus MCHBAR writes 
On these CPUs the MCHBAR window is 16KiB large. This code was just
copied from SNB.

Change-Id: I263cfc678a2eb8eeee8ab9157c749359064a9be8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-10-06 10:11:20 +00:00
Kyösti Mälkki
f9891c8b46 kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset 
The extra PCI bus RST# and 200ms delay there was workaround
for custom add-on hardware.

Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2019-10-05 13:21:55 +00:00
Kyösti Mälkki
ad787e18e0 intel/i945,i82801gx: Refactor early PCI bridge reset 
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-10-05 13:21:00 +00:00
Kyösti Mälkki
beceea29d1 sb,nb/intel/fsp_rangeley: Rename from xx_DEV_FUNC 
Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.

Change-Id: I6ead2bc5e41a86c9aeef730f5664a30406414c8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-10-05 05:06:12 +00:00
Kyösti Mälkki
2647b6f9ba intel/i945: Define peg_plugin for potential add-on PCIe card 
Change-Id: I06f6a7ed7a1ce935d154b8c7b11dcb81608329b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-10-01 01:56:17 +00:00
Kyösti Mälkki
9137cbd5e4 intel/i945: Delay bridge VGA IO enable to ramstage 
Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-10-01 01:55:01 +00:00
Kyösti Mälkki
444d2af9a9 intel/i945: Define p2peg for PCIe x16 slot 
Change-Id: I0e9dd06376c1076be4a4c41ff87dfd3cf820d7bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-10-01 01:54:23 +00:00
Kyösti Mälkki
df128a55b1 intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL 
This is a PCI standard register, no need to alias its
definitions under different names.

Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-10-01 01:54:08 +00:00
Kyösti Mälkki
23d4d9f368 amdfam_10h-15h: Use ENV_PCI_SIMPLE_DEVICE 
Change-Id: I265d50af1099ae4449b5adebcf21e2043aa02c7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35654
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-29 03:39:33 +00:00
Kyösti Mälkki
f485d91141 nb/via/vx900: Remove some __SIMPLE_DEVICE__ use 
Change-Id: I840131f91e79c740c0c8784c252723ae90ded458
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-09-28 21:16:02 +00:00
Kyösti Mälkki
d7205bebd5 nb,sb/intel: Clean up some __BOOTBLOCK__ and __SIMPLE_DEVICE__ use 
Change-Id: Ie3f3c043daa6ec18ed14929668e5acae172177b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-09-28 21:15:27 +00:00
Kyösti Mälkki
197a3c6cea nb/intel/x4x: Avoid x4x.h header with romcc-bootblock 
Change-Id: If8b70298bffd72d1de7f74917131d648c5fcab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-09-28 21:15:02 +00:00
Kyösti Mälkki
e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER 
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-24 22:56:52 +00:00
Patrick Rudolph
2a93d288a8 nb/intel/nehalem: Enabled VBOOT support 
Tested on Lenovo T410.

Change-Id: I86100be79bf2337d65b688edba34b87f3ac18cb6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
 2019-09-20 07:17:27 +00:00
Arthur Heymans
ca24fe48c4 nb/nehalem: Move MMCONF_BASE_ADDRESS to a common place 
Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-17 08:18:00 +00:00
Elyes HAOUAS
10348399a6 {i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h> 
Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34934
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-15 20:42:34 +00:00
Elyes HAOUAS
deda9c0f8a northbridge: Remove unused include <device/pci_ops.h> 
Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33529
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-15 20:39:59 +00:00
Elyes HAOUAS
1e3d16e8d1 nb/i945: Remove unused include <cpu/cpu.h> 
Change-Id: I5dff9b7c157b2aba596e95b5fb18a84f7c4e9365
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-09-15 20:35:14 +00:00
Kyösti Mälkki
7f50afb0c7 drivers/elog: Add elog_boot_notify() 
Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2019-09-13 09:58:33 +00:00
Kyösti Mälkki
2cce24dd4b intel/nehalem: Refactor ACPI S3 detection 
Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-09-13 09:58:18 +00:00
Elyes HAOUAS
c27014b9df src/{northbridge,soc}: Remove not used #include <elog.h> 
Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-09-12 13:16:10 +00:00
Angel Pons
18a55cdd49 nb/intel/nehalem: Add a header for raminit_tables.c 
This is necessary to get rid of a .c include.

Also do some cosmetic fixes to a table, now that the line length limit
has been raised.

Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2019-09-12 13:15:25 +00:00
Arthur Heymans
8bb2bace86 nb/intel/x4x/raminit: Move dummy reads after JEDEC init 
Vendor only does dummy reads right after JEDEC init is finished
and dram init was marked as finished.

Dummy reads also make much more sense after JEDEC init as a way to
send a few JEDEC commands, presumably as a way to make sure it is
ready.

TESTED on ga-g41m-es2l (still boots fine)

Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2019-09-06 00:15:02 +00:00
Kyösti Mälkki
540151f115 intel/haswell: Use smm_subregion() 
Change-Id: Idfb13ab03d4d4ae764bdda62a29848db9d8dcd81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34737
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-08-28 22:52:47 +00:00
Kyösti Mälkki
d53fd704f2 intel/smm/gen1: Use smm_subregion() 
Change-Id: I371ed41f485b3143e47f091681198d6674928897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-08-28 22:51:27 +00:00
Kyösti Mälkki
cd7a70f487 soc/intel: Use common romstage code 
This provides stack guards with checking and common
entry into postcar.

The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.

Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-08-26 21:08:41 +00:00
Nico Huber
4a86b3b036 nb/intel/gm45: Call ddr3_calibrate_zq() only for DDR3 :) 
Change-Id: I7d00ddf727e7250b767a1c4b58bf11b17e900fc1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34828
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-08-26 07:12:13 +00:00
Kyösti Mälkki
c99d3afe3e amdfam10: Remove use of __PRE_RAM__ 
Change-Id: I4215b27332034a3c07052db92e4abae55c3fe967
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-08-26 02:08:42 +00:00