Subrata Banik
8c4aa15e91
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
...
Enable PCIE RP1 to fix DEKEL FW download failed for x4
controller (PEG 0:6:0).
Enable PCIE RP3 to fix HSPHY FW download failed for x8
controller (PEG 0:1:0)
BUG=b:176940923
TEST=No FSP error seen while loading DEKEL, HSPHY FW.
Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-01-10 17:49:27 +00:00
Subrata Banik
85144d9002
soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
...
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 17:49:19 +00:00
Angel Pons
9a1b720b1f
soc/intel/broadwell: Use mp_cpu_bus_init
...
This is needed to allow switching to Haswell CPU code in the future.
Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46886
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 16:11:32 +00:00
Nico Huber
03d9298490
superiotool/nuvoton: Set NCT6791D GPIO inputs to NANA
...
There were several default values given for GPIO data and status
registers. As all GPIO are configured as inputs by default, we
can't predict the values of these registers, hence set their
default values to NANA.
Change-Id: I0507dd75e0f2a5c7e4d2e9cdbe1f860b544deac3
Signed-off-by: Nico Huber <nico.h@gmx.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Clay Daniels <clay.daniels.jr@gmail.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-10 15:49:24 +00:00
Angel Pons
15e5e51461
cpu/intel/haswell/haswell.h: Align with Broadwell
...
Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 15:43:10 +00:00
Angel Pons
4c95f10232
cpu/intel/haswell: Align cosmetics with Broadwell
...
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3eb522a48edf9e8fc7664141253ae4e2072d71fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46913
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 15:43:03 +00:00
Angel Pons
829fb2e985
cpu/intel/haswell: Do not determine CPU type at runtime
...
It is already known at compile-time.
Change-Id: I20303cd1f79b71268a9d734c85a1291afe9177e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46912
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 15:42:17 +00:00
Angel Pons
78c45bd3ef
sb/intel/bd82x6x: Use PCH_LPC_DEV macro
...
Change-Id: I681bb126546b5a7bda3f1bac05c345d2cf60b178
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-01-10 15:42:05 +00:00
Kyösti Mälkki
732eaf20c3
util/autoport: Rename to mainboard_fill_gnvs()
...
Change-Id: Ia8d7083ca2f21abbb5f184c1b55dcf1bf047a7be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-10 11:42:30 +00:00
Kyösti Mälkki
388c16a7e8
mb/google/cyan: Move board_id() to mainboard_fill_gnvs()
...
Only a google/cyan variant evalutes BDID in ASL.
Change-Id: I3d839333333b4762ae5350734c85471a3c12838a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49003
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:41:32 +00:00
Kyösti Mälkki
98323cd222
ACPI: Add missing include in nvs.h
...
Change-Id: Ic779a668ebaa4f0c9bdef95fd6de8f0179e8a534
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49004
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:40:45 +00:00
Kyösti Mälkki
c2b0a4fa32
soc/intel: Rename to soc_fill_gnvs()
...
Replace acpi_create_gnvs() under soc/ to reflect their
changed funcionality.
Change-Id: I7bdbe0d6f795252e713e9785ada2b6320e6604b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48717
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:40:22 +00:00
Kyösti Mälkki
999e441338
soc/intel: Replace acpi_init_gnvs()
...
Rename these to soc_fill_gnvs() and move the callsite away
from mb/.
Change-Id: I760c36f65c6122103f2be98fc11ee13832c2772e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48716
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:39:28 +00:00
Kyösti Mälkki
a9766c7ada
mb/x/acpi_tables: Rename to mainboard_fill_gnvs()
...
Rename acpi_create_gnvs() functions under mb/ to reflect
their changed functionality.
Remove now empty mb/acpi_tables.c files.
Change-Id: Ia366867ef73d1ade9805dc29b8e14b3073f44f60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48707
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:29:10 +00:00
Kyösti Mälkki
8a5f157fdf
sb/intel: Use acpi_inject_nvsa()
...
Change-Id: I5f1762c4a25631af9d29a2cb038620d9e9698f8b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48715
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:27:40 +00:00
Kyösti Mälkki
4b4e995988
sb/intel: Factor out soc_fill_gnvs()
...
Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:27:06 +00:00
Kyösti Mälkki
9f441dfc70
ACPI: Replace uses of CBMEM_ID_ACPI_GNVS
...
Change-Id: I45a2d9cb7f07609a1ff03fd70f17c3f2d4f013b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:25:12 +00:00
Kyösti Mälkki
46e37c6343
soc/intel/braswell: Refactor acpi_init_gnvs()
...
Move GNVS details to different function, called
from acpi_create_gnvs().
Change-Id: Ief02c078fe37753c0d29418394a351105a1aacc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48704
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:23:07 +00:00
Kyösti Mälkki
82f6b932e9
mb/x/acpi_tables: Move EC_RW detection
...
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.
Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:18:05 +00:00
Kyösti Mälkki
d77b5e9f99
ACPI: Drop redundant ChromeOS setup for GNVS
...
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:16:55 +00:00
Kyösti Mälkki
81b8472237
ACPI: Drop redundant CONSOLE_CBMEM setup in GNVS
...
Already done from common gnvs_get_or_create() implementation
after gnvs_cbmc_ptr() is defined.
Change-Id: I77c292cd9590d7fc54d8b21ea62717a2d77e5ba4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48702
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:16:26 +00:00
Kyösti Mälkki
3139c8dc05
ACPI: Drop redundant CBMEM_ID_ACPI_GNVS allocations
...
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-10 11:15:10 +00:00
Felix Singer
fb777b5da8
mb/google/parrot: Replace while-loop with do-while
...
Fixes linter error complaining about trailing semicolon.
Change-Id: I3f74f25cb2e3edcdd509abd86d80098241c05741
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-09 16:31:29 +00:00
Felix Singer
57ef7c37d8
mb/google/parrot: Let else statement follow closing brace
...
Fixes a linter error.
Change-Id: I1302e32b0d52e37d9cb4503128edc7d1df1c3bd8
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-09 15:22:37 +00:00
Felix Singer
81ffd00856
mb/google/parrot: Get rid of hard-coded function names in printks
...
Instead of hard-coding function names in strings, use the __func__
constant for better maintainability.
Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-09 15:22:11 +00:00
Felix Singer
98b51f4cf9
mb/google/parrot: Fix spacing issues
...
Add a space after each comma to fix linter issues.
Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-09 15:20:52 +00:00
Felix Singer
32d893bfbb
mb/hp/pavilion_m6_1035dx: Replace leading spaces with tabs
...
Replace leading spaces with tabs so that linter doesn't complain. Also,
remove an unneeded empty line.
Change-Id: I5809c1ca13782393cb4c4051a7061186c1c144e4
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-09 15:20:38 +00:00
Felix Singer
a4ee796115
mb/hp/pavilion_m6_1035dx: Replace (foo*) with (foo *)
...
Change-Id: Iff38caf5f4a4d25f4bafdd821c51de24f54e3ce5
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-01-09 15:20:05 +00:00
Felix Singer
c299123608
mb/hp/pavilion_m6_1035dx: Put opening braces in previous line
...
Put opening braces in previous line to fix linter errors.
Change-Id: I7bd49393056f80ce4f6078c646db46c2a67f2381
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49234
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-09 15:19:53 +00:00
Felix Singer
5ad019b092
mb/hp/pavilion_m6_1035dx: Remove trailing semicolon from macro
...
Macros should not use a trailing semicolon.
Change-Id: Ibbcd589c7afa72e9e468e5f4b557bb2c665bbec0
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-01-09 15:19:14 +00:00
Felix Singer
21dd4793b4
mb/hp/pavilion_m6_1035dx: Fix spacing issues in mptable.c
...
Align the bytes of picr_data[] and intr_data[] with 8 bytes per line and
add spaces after commas so that the linter doesn't complain.
Also, remove spaces before the postfix '++' operator.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I90bec7fdfabca6f8afd1508c673241e0742e2ee9
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49191
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-09 15:18:59 +00:00
Felix Singer
21106e3505
vc/intel/fsp1_1/skylake: Remove unused header file
...
Change-Id: I329a1484cbd16296a2aa047876c2506c74d4452d
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-09 14:45:02 +00:00
Felix Singer
7722dc32d1
mb/asrock/h110m: Drop VR configuration from devicetree
...
Drop VR configuration since it matches the platform defaults.
Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-01-09 14:44:13 +00:00
Felix Singer
5b256dfad6
mb/asrock/h110m: Remove zeroed options from devicetree
...
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Ic39b4c70ccb9ec21780c937322d63820064abbd1
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49185
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-09 14:43:35 +00:00
John Zhao
9c1a335fbc
mb/google/volteer: Configure Delbin USB2 ports for Type C
...
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com >
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 22:01:26 +00:00
Felix Held
e862a004d7
util/amdfwtool,post: add missing distclean target
...
Without this target some spurious errors occurred when running make
distclean at the top level of coreboot.
Change-Id: I3d3061b386fc5b4a043cfc7ff8fd3c0da33c0e83
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49227
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 21:10:51 +00:00
Felix Held
f9608cd8f4
soc/amd/picasso: add missing GNB I/O APIC initialization
...
Change-Id: Iddb0c20e769e6921ba5d0dd4a84ab9e494d522e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48269
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 15:18:18 +00:00
Marshall Dawson
663c17c78d
amd_blobs: Advance pointer for picasso FSP 0x25
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Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Change-Id: I2aa5f353432cd8f79005153a06ac35c1e654f6f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-01-08 15:18:07 +00:00
Marco Chen
07c80b2164
mb/google/octopus: add audio codec into SSFC support for Bobba
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BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com >
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org >
2021-01-08 14:29:31 +00:00
Tzung-Bi Shih
3f80a7aa6d
mb/google/asurada: Support audio
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- Turns audio-related things power on.
- Selects I2S pin-muxing.
- Exposes GPIO "speaker enable" for switching on and off.
BUG=b:176856418
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org >
Change-Id: If595657bbddad85bc9a154b3648bae1190cb00b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2021-01-08 08:31:32 +00:00
Seunghwan Kim
3436bb03f6
mb/google/dedede/var/sasuke: Add internal USB camera support
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This change adds internal USB camera into devicetree for sasuke
BUG=None
TEST=Built and checked camera device existence with lsusb
Change-Id: I51b9bb174205d984f1d060afd603f1d087095645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 08:30:05 +00:00
Seunghwan Kim
9c5a3cbc0d
mb/google/dedede/var/sasuke: Enable ELAN touchpad
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This change adds ELAN touchpad into devicetree for sasuke.
BUG=None
TEST=Built and verified touchpad function
Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2021-01-08 08:29:44 +00:00
Seunghwan Kim
c6466aa893
mb/google/dedede/var/sasuke: Enable audio feature
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This change adds DA7219 audio codec and MAX98360A amplifier for sasuke.
BUG=None
TEST= Built and heared speaker sound on OS
Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2021-01-08 08:29:31 +00:00
Seunghwan Kim
07339a5c21
mb/google/dedede/var/sasuke: Configure GPIO NC pads
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Configure GPIO NC pads for sasuke.
BUG=b:172104731
TEST="FW_NAME=sasuke emerge-dedede coreboot"
Change-Id: I3bf8f97708536010da82402ea3d49e387e732d61
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2021-01-08 08:29:22 +00:00
Felix Singer
9486b1dba6
mb/asrock/h110m: Drop DEVICETREE from Kconfig
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Drop DEVICETREE from Kconfig since it matches the default value.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2021-01-08 08:28:36 +00:00
Felix Singer
c3c8bed057
mb/clevo/cml-u: Drop VGA_BIOS_FILE from Kconfig
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It doesn't make sense to configure that filename in Kconfig, since the
filename can be changed by the user. So remove it.
Change-Id: I3eed05637da29096bc1d134505d7335db5db1439
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 08:28:16 +00:00
Jakub Czapiga
dd85c82962
tests: Add lib/fmap-test test case
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Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Change-Id: I885ea05d509d3b1330de7a18531f310d290c6965
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2021-01-08 08:26:26 +00:00
Marco Chen
525cc4626a
ec/google/chromeec: add SSFC CBI support
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An API is added to get SSFC value from cros EC.
BUG=b:174118027
BRANCH=octopus
TEST=check SSFC value from EC is correct compared to value in CBI
Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1
Signed-off-by: Marco Chen <marcochen@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jett Rink <jettrink@google.com >
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org >
2021-01-08 08:25:42 +00:00
Furquan Shaikh
d3b7e2f94a
soc/intel/common/uart: Restrict scope of uart_common_init to uart.c
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uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h
Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 08:24:38 +00:00
Furquan Shaikh
fb29ca0c55
soc/intel/common: Pass in pci_devfn_t into lpss_set_power_state
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This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.
Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-01-08 08:24:20 +00:00
