Zheng Bao
4bf6f49d12
amdfwtool: Move soc_id to cb_config
...
Save the soc_id into a global struct.
Change-Id: I2a0f04a09635086e3076a97b535df8a19d0693ce
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72450
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-10 12:45:00 +00:00
Fred Reitberger
c4f3a33e49
util/amdfwtool: Add UMSMU blob support
...
Add PSP blob Type 0xA2 uMsmu support.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com >
Change-Id: Ib38ec03bf20f46774f7438b21d18704cc1ec57fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: ritul guru <ritul.bits@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-02-09 20:43:36 +00:00
Zheng Bao
29063fbd7d
amdfwtool: Parse the line with SOC_NAME
...
We need to put soc name to fw.cfg for future combo feature.
We skip for now when SOC_NAME is found.
1/5
of split changes https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: I2b8d7154d22db13675ff57b6abe61c747604c524
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-09 13:45:51 +00:00
Zheng Bao
3d7623ffc9
amdfwtool: Add SOC family definition for Carrizo
...
For Carrizo, the soc name was set as UNKNOWN.
The change is supposed to be binary unmodified, except the SPI
settings. According to the spec, the Stoneyridge and Carrizo have the
same definition of SPI setting in EFS.
Change-Id: I9704a44773b2f541f650451ed883a51e2939e12a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-09 13:44:39 +00:00
Zheng Bao
4e8fb3503c
amdfwtool: Allow the location to be a relative address
...
When the BIOS size is more than 32M, the physical address of EFS
header will be complicated, like 0xfe020000 or 0xfc020000. So we make
it simpler to allow to use relative address.
This CL works with https://review.coreboot.org/c/coreboot/+/69852
TEST=Result image is binary same on
amd/birman amd/majolica amd/gardina amd/mandolin
Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-09 13:04:08 +00:00
Martin Roth
0363561a30
util/testing: Allow scanbuild test to be skipped
...
This is currently killing the jenkins builds. This patch allows it to
be disabled until the reason is found.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I16dba80a88953aa95f7f647ba12b2ec3297ab81f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-02-08 19:15:40 +00:00
Zheng Bao
7c7294fa27
amdfwtool: Report the address of EFS header and body
...
The address mode is an internal mode which AMD FWs use. Regular
developers don't have to know that. Just report the relative address
every time. For the cases head and body are split, the address of body
is also reported.
Change-Id: I77d9aac0b3d996363341c1d2dae049ec344b39aa
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-08 12:26:37 +00:00
Martin Roth
1b74898395
util/abuild: Add flags to allow abuild to skip boards
...
This change adds 2 command line parameters, --skip_set and --skip_unset
that allows abuild to skip boards with particular Kconfig values either
set or not set.
Note that it only works on BOOL type variables.
This can be set on the abuild command line, or the JENKINS_ABUILD_OPT=
variable on the make command line.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I43336484cf25f83065ec7facf45c123d831024b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2023-02-07 23:33:39 +00:00
Alexander Goncharov
893c3ae892
tree: Drop repeated words
...
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com >
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-07 04:37:31 +00:00
Martin Roth
0cbc3528e5
util/docker: Add libgpiod-dev to coreboot-sdk for flashrom
...
Flashrom needs libgpiod-dev to build the new bitbanging programmer
driver for Linux libgpiod.
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: I88f7e11fab115487cc44d4b89b3eab4745ad058d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org >
2023-02-06 12:44:31 +00:00
Zheng Bao
4044e85938
amdfwtool: Add phoenix and glinda in get_psp_fw_type
...
Change-Id: If80cc5396703cef41cc615008c9f0dac0b7bbb09
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2023-02-06 12:28:06 +00:00
Zheng Bao
1d7fa216ba
amdfwtool: Remove useless printing out
...
Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72724
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-05 01:10:46 +00:00
Zheng Bao
7db7642a85
amdfwtool: Add a function to make the calling stack less deep
...
And make less levels of indentations in the code.
Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-05 01:08:55 +00:00
Martin Roth
4bd2325802
util/scripts/testsoc: Pass arguments to abuild
...
This allows the user to pass one or more arguments through the testsoc
script to abuild.
Example:
testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN"
Signed-off-by: Martin Roth <gaumless@gmail.com >
Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-05 00:51:38 +00:00
Felix Held
9f5a5eefc3
util/amdfwtool: add comment about reused PSP firmware type 0x5f
...
On family 15h and 16h processors with PSP, the PSP firmware type 0x5f
corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this
corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to
clarify this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Bao Zheng <fishbaozi@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-02-04 03:15:37 +00:00
Arthur Heymans
bc3261f828
util/autoport: Use chipset.cb references
...
TESTED with x220 logs.
Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jakub Czapiga <jacz@semihalf.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
2023-02-04 01:42:43 +00:00
Zheng Bao
85ee1fd571
amdfwtool: Add entry RIB whose subprog equals 1
...
For the PHX, it uses subprog 0.
For the PHX2, it uses subprog 1.
Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-02-04 01:42:13 +00:00
Fred Reitberger
abce429dac
util/scripts/testsoc: Only select mainboards
...
The testsoc script was pulling in odd results when the -K option matched
options in sources, Makefiles, and device trees. Adding another grep to
limit the list to just Kconfig matches ensures that only actual
mainboards are built.
TEST="./util/testsoc -K PICASSO" no longer tries to build mainboard "0"
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com >
Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72655
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-03 13:57:07 +00:00
Tarun Tuli
5044dc48f3
util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOL
...
In order to support logging events for when we show early signs
of life to the user during CSE FW syncs and MRC trainings add
support for the ELOG_TYPE_FW_EARLY_SOL type.
BUG=b:266113626
TEST=verify event shows in eventlog CSE sync/MRC training
Change-Id: I3913cb8501de9a2605266cf9988a7195576cb91d
Signed-off-by: Tarun Tuli <tarun.tuli@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71296
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2023-02-02 21:44:13 +00:00
Zheng Bao
cc132038e2
amdfwtool: Set the level of RIB file as level 2
...
It is about AB recovery layout which only has level 2.
Change-Id: I836f11ca0bf5ad37e5093419465244a5c83318cb
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-02-02 13:43:59 +00:00
Patrick Rudolph
ef5ebdb5bb
ifdtool: Introduce region_name_fmap
...
Instead of directly accessing the region_name array use a helper
function. This allows to move the region name array to a separate
file.
Change-Id: Ifc810da1628cebd2728d0185502c462ff9428597
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
2023-02-02 13:22:00 +00:00
Patrick Rudolph
1920900baa
ifdtool: Add missing chipset_name
...
Add denverton soc chipset name.
Change-Id: I0fd8494123490d6ccc21af2ed30c30d50ddb4e8e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68693
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-02 13:21:07 +00:00
Patrick Rudolph
09b136cfe8
ifdtool: Drop chipset without IFD
...
Drop unused chipsets that do not use an IFD.
Change-Id: I999e5e5d2063b8d33819fb22296ed486e1194cbb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2023-02-02 13:20:19 +00:00
Patrick Rudolph
be25f96c2d
ifdtool: Cleanup IFDv1 detection
...
Change https://review.coreboot.org/c/coreboot/+/54305 "util/ifdtool:
Use -p platform name to detect IFDv2 platform and chipset" made
the '-p' argument mandatory for IFDv2 platforms.
Drop the IFDv2 platform CHIPSET_C620_SERIES_LEWISBURG from IFDv1
detection.
Change-Id: If29f8718b7aa696cdc07deef4c98be9a68c66f10
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68680
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-02 13:19:36 +00:00
Patrick Rudolph
16598745b8
util/ifdtool: Add Wellsburg support
...
Wellsburg is IFDv2 compatible in most fields, but not in all.
It only has 8 regions and the flash master bits match the defines for
IFDv1 and thus has an "IFDv1.5" descriptor.
Add a new enum for IFDv1.5 descriptor and use them to properly operate
on this IFD.
The 'SPI programming guide' is inconsistent and mentions 6 regions
in one place, but 7 regions in another chapter. Tests showed that it
actually supports 7 regions.
Add support using the -p argument to specify Wellsburg platform.
The previous patch made sure that only 8 regions are used and that no
corruption can happen when operating in IFDv2/IFDv1.5 mode.
Tested on Intel Grangeville.
Documents used:
Intel Document Id: 516552
Intel Document Id: 565117
Change-Id: I651730b05deb512478d059174cf8615547d2fde4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Co-developed-by: Julian Elischer <jrelis@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
2023-02-02 13:19:11 +00:00
Zheng Bao
7c558d0cfa
amdfwtool: Remove the duplicated entry RIB
...
It should be PSP_RIB_FILE which is already there.
Change-Id: Ie7471489bd34554e357510b04473102d002f9988
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72506
Reviewed-by: ritul guru <ritul.bits@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-02-01 13:44:02 +00:00
Elyes Haouas
b63eb4d172
crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
...
Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2023-02-01 06:06:36 +00:00
Elyes Haouas
e2cbeebe9f
crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2
...
Change-Id: Iaf0988997c6644e0e4f02d60a1d6de0e498e19bc
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71889
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-02-01 03:12:03 +00:00
Arthur Heymans
15d5183e4a
util/sconfig: Remove lapic devices from devicetree parsers
...
This is all handled at runtime now, so there is no need to have the
ability to statically add lapics to the devicetree.
Change-Id: I0746eb808a2956ac75f76c8189a9ecf190e33ce9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69378
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-01-31 15:22:24 +00:00
Elyes Haouas
2c1511a461
crossgcc: Upgrade mpfr from 4.1.1 to 4.2.0
...
Changes: https://www.mpfr.org/mpfr-current/#changes
Change-Id: Ife757d7a8247c11338ca795109044cdccdf86733
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2023-01-31 13:50:18 +00:00
Elyes Haouas
d15a9f9b34
crossgcc: Upgrade mpc from 1.2.1 to 1.3.1
...
Change-Id: I2d98c3b4c7edaf3ff097f5739c7cc0cd13592e91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2023-01-31 13:48:59 +00:00
Elyes Haouas
8d50e42a51
crossgcc/buildgcc: Add missing "\" at build_NASM
...
"\" is missing at the end of CC line for build_NASM.
Change-Id: Ic29ee731def31f958f939efe19bdb55b503eb6ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2023-01-31 13:47:30 +00:00
Elyes Haouas
6ac0a46bbf
util/crossgcc/buildgcc: Remove extra "/" at the end of IASL_BASE_URL
...
Change-Id: I8df1d93a8b0a0d562c7ae5a9f1a70f2eb26499c9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71976
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-01-30 16:21:27 +00:00
Zheng Bao
dd4c5421d1
amdfwtool: Update and extend PSP header format description
...
The comment in the header amdfwtool.c was written long time ago and is
needed to get updated.
Change-Id: I6f64c9a240503f9d0bf240916c1066944fa39d27
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-01-27 19:52:41 +00:00
Kapil Porwal
0b6954b8d5
elogtool: Fix potential buffer overrun
...
BUG=b:239110778
TEST=Make sure that the output of elogtool is unaffected by this change.
Signed-off-by: Kapil Porwal <kapilporwal@google.com >
Change-Id: Ia1a6341abd834dd9ad5f12c9f2eefb0489364a08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72099
Reviewed-by: Subrata Banik <subratabanik@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-01-27 15:00:20 +00:00
Zheng Bao
92c920b730
amdfwtool: Remove comment "fallthrough"
...
Fix the comment as "checkpatch" says.
Change-Id: Ifa5d7de037aa7024779f3aa4a5d2f5033eed264a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71648
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2023-01-25 14:32:12 +00:00
Christian Walter
1364ac3478
util/inteltool: add support for EBG (Emmitsburg) PCH
...
EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset.
Its datasheet is Intel doc# 606161.
Add Intel Emmitsburg PCH GPIO pin definitions.
Also common code change is made to support Intel Emmitsburg PCH:
a. Instead of 2 PAD registers per GPIO, it has 4 PAD registers.
b. The register address space may not be contiguous from one GPIO
group to the next GPIO group.
Change-Id: Ia0d9179544020b6abb0be1ecd275a9a46356db8a
Signed-off-by: Jonathan Zhang <jonzhang@meta.com >
Signed-off-by: Christian Walter <christian.walter@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: David Hendricks <david.hendricks@gmail.com >
2023-01-24 12:47:30 +00:00
Zheng Bao
99945dcb8c
amdfwtool: Change the variable name to body_location
...
The dir_location and efs_location have the same meaning. Now the dir
means body.
Change-Id: I02d4dc848f189449b6f0a1eea5cd6b8020a7d101
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-01-22 19:00:43 +00:00
Zheng Bao
3d426f38c5
amdfwtool: Add instance = 0 for bios image
...
For future BIOS image entry whose instance = 1.
Change-Id: Iaa40872b270cf9ff289794c8c51c4d8b448d862d
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-01-22 18:56:52 +00:00
Zheng Bao
de6f198619
amdfwtool: Add missing code for checking new family phoenix & glinda
...
Change-Id: Ib82f6c03b93d277f3f7f27ce57c1a41fdc103575
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-01-22 18:55:36 +00:00
Zheng Bao
8eba6625ce
amdfwtool: Add entry types required to support glinda & phoenix SOC
...
Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: ritul guru <ritul.bits@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2023-01-22 18:34:21 +00:00
Felix Singer
ad6e3c847f
tree: Drop Intel Ice Lake support
...
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.
As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.
This affects the following components and their related code:
* Intel Ice Lake SoC
* Intel Ice Lake CRB mainboard
* Documentation
Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-01-19 01:26:36 +00:00
Nicholas Chin
8ef2f7c77c
util/kconfig: Add comment explaining difference from upstream
...
coreboot adds a patch on top of upstream Kconfig which allows the
generated Kconfig dependency files to be placed in a separate
directory than the autoconfig files based on the KCONFIG_SPLITCONFIG
variable. Add a comment to explain this difference.
Change-Id: Ief38ab84f852ff24f896ec8bbf094aa737a172d9
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-01-15 17:59:39 +00:00
Nicholas Chin
6e902bcfcb
util/kconfig: Fix patch to be compatible with quilt
...
The patch added in commit b7f92a0b6anic.c3.14@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
2023-01-15 17:58:53 +00:00
Martin Roth
20646cdbe8
soc/amd: Change Morgana codename to Phoenix
...
Now that the next generation of APUs is officially announced, we can
unmask morgana.
The chip formerly known as Morgana is actually Phoenix.
Surprise!
This patch just changes the name across the entire codebase.
Note that the fw.cfg file will stay pointing to the
3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is
updated.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com >
Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2023-01-12 03:13:17 +00:00
Sergii Dmytruk
2710df765b
treewide: stop calling custom TPM log "TCPA"
...
TCPA usually refers to log described by TPM 1.2 specification.
Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022
Ticket: https://ticket.coreboot.org/issues/423
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
2023-01-11 16:00:55 +00:00
Felix Singer
16a444c501
util/crossgcc/Makefile.inc: Terminate quoted string
...
`make help` does not execute successfully because a quoted string is
unterminated. Fix that.
Change-Id: I643fde1270a154ba523eb21522dcf5f6d4023110
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Elyes Haouas <ehaouas@noos.fr >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
2023-01-11 15:36:08 +00:00
Pratikkumar Prajapati
c262b44d7c
utils/inteltool: Add support to print Key Locker status
...
Add command-line option "-k" to print status.
Sample output:
$ inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : NO
===========================================================
Change-Id: Icb1b08619b1dbc535640127f7ab5f6b49d70a6fe
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com >
2023-01-10 14:43:22 +00:00
Patrick Rudolph
98ecaa4a55
ifdtool: Determine max regions from IFD
...
IFDv1 always has 8 regions, while IFDv2 always has 16 regions.
It's platform specific which regions are used or are reserved.
The 'SPI programming guide' as the name says is a guide only,
not a specification what the hardware actually does.
The best to do is not to rely on the guide, but detect how many
regions are present in the IFD and expose them all.
Very early IFDv2 chipsets, sometimes unofficially referred to as
IFDv1.5 platforms, only have 8 regions. To not corrupt the IFD when
operating on an IFDv1.5 detect how much space is actually present
in the IFD.
Fixes IFD corruption on Wellsburg/Lynxpoint when writing a new
flash layout.
Change-Id: I0e3f23ec580b8b8402eb1bf165e3995c8db633f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
2023-01-10 13:55:17 +00:00
Felix Singer
b3ebf5ba0b
util/liveiso: Update from 22.05 to 22.11
...
Update and also adjust configs so that they work with NixOS 22.11.
Change-Id: Ia0fed68f5449ccf56b25660f5cdbc8c239064748
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin L Roth <gaumless@gmail.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2023-01-10 07:20:29 +00:00
