This change adds new Rembrandt SoC support by defining it as base SoC
of sabrina as sabrina is derived from Rembrandt SoC.
All the needed changes for Rembrandt SoC will be applied under
SOC_AMD_REMBRANDT config.
Change-Id: I1c9392918cc2c6b511d467f99aceefc725750ce6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new folder and basic drivers for Mediatek SoC 'MT8188'.
Difference of modules including in this patch between MT8188 and
existing SoCs:
Timer:
Similar to MT8195 and MT8186, MT8188 uses v2 timer.
EMI/PLL/SPI:
Different from existing SoCs.
The implementation is based on these files:
MT8188G_Application Processor Technical Brief_v0.4.pdf
MT8188G_Functional Specification v0.4.pdf
MT8188 Application Processor Registers-1.pdf
MT8188 Application Processor Registers-2.pdf
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3320f3d49a9b9ed781ceb812e4341e379db4ac20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65585
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:237263080
TEST=Able to build and boot MTL simics. Also, verified the FSP debug
log is using coreboot debug library as below:
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle
is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80ba73afed642e6d21c5310e9bf734f6f7170347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add memory init with placeholder to fill in required memory
configuration parameters. DQ map and Rcomp can be auto probed by
the FSP-M hence, kept it as default.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Able to boot till FSP-M/MRC using MTL simics.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definitions for the GPIO pins on Meteor Lake SoC,
as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following GPIO communities and GPIO groups:
Comm. 0: GPP_CPU, GPP_V, GPP_C
Comm. 1: GPP_A, GPP_E
Comm. 3: GPP_H, GPP_F, SPI0, VGPIO3
Comm. 4: GPP_S, JTAG
Comm. 5: GPP_B, GPP_D, VGPIO
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I7fe9654f22b074a9af18eb7bcdc21812dee77035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64169
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the CSE FW update flow, update is triggered when there is a mismatch
in CSE versions. CSE RW blob is directly mapped from SPI flash, hashed,
compared and then the CSE RW region is updated. However, in the case of
compressed blobs, we cannot directly map the blobs from SPI. It needs to
be decompressed before the hash is calculated and compared. Add a check
for compressed blobs and figure out whether it needs to be directly
mapped from SPI or loaded into memory allocated for file in CBMEM, with
the provided CBMEM ID.
BRANCH=firmware-brya-14505.B
Change-Id: I3bc7708c95272e98702bc25b2334e6e64a93da8a
Signed-off-by: Krishna P Bhat D <krishna.p.bhat.d@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CSE FW sync is currently performed in romstage, when uncompressed ME_RW
blobs are used. When compressed blobs are used, this has to be done in
post-RAM stages. Add Kconfigs to describe when the CSE FW sync will be
performed, in romstage or in ramstage.
BRANCH=firmware-brya-14505.B
Change-Id: Iac37aaa5ede5e1cd2d76a58ce2db9cb5b8f42398
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65366
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In
order to support them with the new firmware where TPM_GOOGLE_TI50 is
selected, use the board rev to determine the EC-is-trusted logic.
BUG=b:237355198
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This change copies ec_commands.h directly from the ChromiumOS EC repo,
with the exception of changing the copyright header to SDPX format.
Update to commit SHA1 2cbf6fbf (ec_commands: Drop VBNV read/write
support).
BUG=b:178689388
TEST=none
BRANCH=none
Change-Id: I74fa8b1171ca109dee163a7657659cdac1687450
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65469
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems fixup or adjustment addition for relocation type
EFI_IMAGE_REL_BASED_DIR64 is missing in the fsp rebasing code. The
patch address the miss. Without extending the fixup for the relocation
type, build system throws warnings during the rebasing of FSP-M and
FSP-S blobs which are built with 64bit.
Portion of build output containing warning with debug enabled cbfs lib:
...................................................
E: file offset: 9218
E: file type = 4
E: file attribs = 0
E: section offset: 9230
E: section type: 12
E: TE image at offset 9234
E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000
E: Relocs for RVA offset 12000
E: Num relocs in block: 18
E: reloc type a offset f40
E: Unknown reloc type: a
Portion of build output after fix:
..................................
E: file offset: 9218
E: file type = 4
E: file attribs = 0
E: section offset: 9230
E: section type: 12
E: TE image at offset 9234
E: TE Image 0xffed80d4 -> 0xff256234 adjust value: ff37e000
E: Relocs for RVA offset 12000^M
E: Num relocs in block: 18
E: reloc type a offset f40
E: Adjusting 0x7f2e7f377024 ffee9192 -> ff267192
E: reloc type a offset f48
TEST: Integrate FSP blobs built with 64 bit and do boot test.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I894007ec50378357c00d635ec86d044710892aab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65383
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Debug FSP is ~850KiB larger than release FSP and we don't have
sufficient space for nissa flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:231395098
TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Intel FSP has "debug" build which is not public, used for debugging by
approved developers. Add a Kconfig to indicate that coreboot is building
with debug version of FSP so we can adjust few things (i.e. flash
layout) in the case.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ibc561498d7edcb9d7ec155f090822f1eb25d10cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65466
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Add ADL-S specific table with IRQ constraints to avoid accessing
non-existent devices.
Also when using debug FSP, silicon init would assert on assigning IRQs
for non-existent devices. This patch fixes the problem.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Due to incorrectly interpreted DOC #630603, the reserved range
remains the same for all ADL platforms and is sync with
src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the
range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was
only mean for static allocations, but the rest is also reserved. The
only difference between ADL-S and other ADL platforms is Trace Hub
base.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:237238786
BRANCH=None
TEST=Build and boot Nivviks.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Based on latest schematic:
1. Update devicetree for USB port description
2. Add touchscreen ILITEK, amplifier ALC1019, codec ALC5682
3. Configure GPIO table to reflect that
4. Remove APW8738BQBI IC so set "disable_external_bypass_vr to "1"
BUG=b:235303242, b:236791101
BRANCH=dedede
TEST=build
Change-Id: I38c8c5b913013d818ac6a26284184c9decdd9f4e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65079
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kernel driver will en/disable the IRQ when suspend/resume. If lock
the pin, driver can't change the status which causes the unexpected
behavior. Device will wake when insert the pen. This is workaround
until we figure out the correct setting for driver.
BUG=b:233159811
TEST=Pen garage wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
