With IOMMU disabled, kernel complains that 'IOMMUv2 functionality not
available on this system'. Enable iommu in devicetree for skyrim proto
board in order to allow kernel to load and initialize IOMMUv2.
BUG=b:232750390
TEST=Boot to Chrome OS on skyrim board, and
grep dmesg for "AMD IOMMUv2 loaded and initialized"
Change-Id: I2f10f5eda8083335619a34c44df253b8e5a8572c
Signed-off-by: Jason Glenesk <Jason.Glenesk@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Enable VBOOT_EARLY_EC_SYNC in coreboot.
EC Sync was failing on ADL-N RVP since the ec image was not getting
stitched into coreboot during emerge build. This is now fixed with https://crrev.com/c/3705002 and hence enabling the EC sync for ADL-N RVP
BUG=b:232875824
TEST=Build and boot adlrvp-n. Ensure EC Software sync is complete.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Ibea37825abd0f13a5184cbbe96c38d44474782f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
This patch ensures all APs finish the task and continue
before_post_cpus_init() if coreboot decides to perform multiprocessor
initialization using native coreboot drivers instead of using
FSP MP PPI implementation.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates choice that lists all possible options to perform
MP Init as below:
1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the microcode loading and reloading API with a
helper function that perform the actual MSR write operation after
taking the microcode pointer from the caller function.
Also, convert the microcode loading failure msg type from `BIOS_INFO`
to `BIOS_ERR` to catch the error in proper.
TEST=Able to perform microcode loading on google/kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9a7cdc2d2c9211f1e0c7921015126f7a1be87761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65249
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures to perform core PRMRR sync if SoC decides to
perform MP Init using coreboot native implementation.
Also, implement a function to allow calling `init_core_prmrr()`
for all CPUs from `before_post_cpus_init()`.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch calls into `intel_reload_microcode() function to load
second microcode patch after BIOS Done bit is set and before
setting the BIOS Reset CPL bit.
Also, remove redundant microcode reloading debug print.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces a newer API to reload the microcode patch when
SoC selects RELOAD_MICROCODE_PATCH config.
Expected to call this API being independent of CPU MP Init regular
flow hence, doesn't regress the boot time.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If480e44b88d04e5cb25d7104961b70f7be041a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Makefile.inc to include five generic LPDDR5 SPDs for the following
parts for Joxer:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I90acb436bccd5dae8585436316246c50fc256842
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds a new CONFIG_VBOOT_GSCVD option that will be enabled by
default for TPM_GOOGLE_TI50 devices. It makes the build system run the
`futility gscvd` command to create a GSCVD (GSC verification data) which
signs the CBFS trust anchor (bootblock and GBB). In order for this to
work, boards will need to have an RO_GSCVD section in their FMAP, and
production boards should override the CONFIG_VBOOT_GSC_BOARD_ID option
with the correct ID for each variant.
BUG=b:229015103
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1cf86e90b2687e81edadcefa5a8826b02fbc8b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
All AMD SoCs which select SOC_AMD_COMMON_BLOCK_I2C also select
DRIVERS_I2C_DESIGNWARE, so make the pairing explicit by moving the
selection into SOC_AMD_COMMON_BLOCK_I2C. This will facilitating adding
the Designware I2C bus ops handler in a subsequent commit.
Change-Id: Ice30c8806766deb9a6ba617c3e633ab069af3b46
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Create the pujjo variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Follow other ADLN variant to generate by manual)
BUG=b:235182560
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_PUJJO
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I73ec985bc19320260d0c3132c1ca23a3648df9e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Convert the librem_14 and librem_mini from using separate devicetrees
to using a baseboard devicetree and overridetrees. This reduces code
duplication, and facilitates adding any new variants with minimal
additional code.
Test: build/boot Librem 14 and Librem Mini v2 boards
Change-Id: Ide65ffc750495c9ba2074757ce467efa2f384c56
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
After commit 63e54275f6 (libpayload: Implement new CBFS access API),
libpayload includes headers from commonlib/bsd, which in turn include
vb2_sha.h from vboot after commit 0655f78041 (commonlib/bsd: Add new
CBFS core implementation). Usually submodules are initialized by the top
level Makefile.inc, but since this file is never read when building
libpayload based payloads outside the main coreboot build, the header
cannot be found unless the vboot submodule had previously been
initialized. This is especially evident when following Tutorial 1 in the
documentation, where the coreboot repo is cloned without recursing into
submodules and coreinfo is built separately from the coreboot build
using `make -C payloads/coreinfo`.
TEST=Deinitialize submodules and run `make -C payloads/coreinfo`.
Coreinfo should build without error.
Change-Id: I29b16525999921fbce51c2459d3d534b64e00b3c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The syscfg has to option to automatically mark the range between 4G and
TOM2, which contains DRAM, as WB. Making it generally not necessary to
allocate MTRRs for memory above 4G if no PCI BARs are placed up there.
Change-Id: Ifbacae28e272ab2f39f268ad034354a9c590d035
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The daughterboard USB 3.0 was set to port 3, which is incorrect. This
patch corrects that to port 4.
This fixes an issue where USB 3.0 devices are not detected when plugged
in to this port.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50f86dee1b512d0dd20d07e3ee17ebfa5e537bc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The USB ports for the Motherboard USB 3.0 and Type-C were labelled
incorrectly. This change swaps the ports, so they are labelled correctly
and also corrects the over-current pins that they use.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80484dc8bdd68dd72b3848720c790d59237a9f8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Hook up C1e FSP S UPD which enables enhanced C-states, to
enhanced_cstates. This allows it to be enabled in the
devicetree with a value of "1" as the default is disabled.
C1e exists on both APL and GLK, and has been there since their
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
