The current early PM setup that attempts to configure dynamic clock
gating relies on PCIe functions to be enabled that may not be.
Instead of reading port 0 or 4 directly to determine the link width
use the register that refelects the soft strapping options as this
will always be available.
Also add a clear register assignment and break for port 0 in the
switch statement instead of falling through to port 4 as that could
end up setting the slot power limit based on port 4 values instead
of based on port 0.
register 0xE1=0x3f and all other root ports should have 0xE1=0x03.
When port 0 and 4 are disabled they will have 0xE1=0x3C before
being disabled by the pch enable handler.
LUMPY default:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 3 0xe1
0x03
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
pci_read8 0 0x1c 0 0xe1
0x3f
pci_read8 0 0x1c 1 0xe1
0x03
Change-Id: I33a37b0ec0c8e570cf5d9dda2c06e0225fee135c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/980
Tested-by: build bot (Jenkins)
Background: The PCI spec (3.0-3.2.2.3.4) requires that PCI devices
implement function 0. The Linux Kernel therefore will not enumerate
a PCI device if it does not present a valid config space at function 0.
If a board does not have anything connected to root port 0 and it is
desired to disable the unused ports in order to save power then this
will cause the other downstream PCIe devices to go missing as they
will not be enumerated.
Intel chipsets provide a way to map root port numbers to different PCI
function numbers, thereby avoiding this issue and allowing root port 0
to be turned off.
This change adds a new chip config option 'pcie_port_coalesce' that
will collapse the enabled root ports into a linear map starting at
zero. This option defaults to disabled as it can have a confusing
effect on the system as the declared static devicetree may not match
what is seen at runtime. This option is also forced on if the static
devicetree disables port 0.
When each root port is processed in the early enable stage it looks
for a lower numbered root port that has been disabled and then swaps
the two assigned function numbers.
However the mapping register is write-once so it has to keep track of
the proposed mapping changes until all ports have been processed
before writing out the final map value. At this point it also updates
the function numbers in the static device tree so they are consistent
with the new layout.
There are a few other closely related fixes in this change:
1) There is a power savings opportunity if an entire bank of ports
(0-3 or 4-7) are disabled. This was checking the chipset revision to
look for CougarPoint B1+ stepping and that was not passing on
PantherPoint where this should always be applied. To fix this I added
a function to determine the chipset type based on comparing the upper
byte of the device ID.
2) Apply the same chipset type check fix to the IOBP programming.
3) There is another power savings opportunity to enable dynamic clock
gating on shared PCIe resources which only applies to ports 0 and 4.
However if 0 or 4 is disabled then the later check to enable this
would fail as that device is already hidden.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
01:00.0 Network controller: Atheros Communications Inc. Device 0030 (rev 01)
02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168B
Change-Id: I828aa407fdc9c156c1c42eda8e2d893c0aa66eef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/979
Tested-by: build bot (Jenkins)
The chipset enforces static-defined interrupt swizzling on PCIe root
ports so if a port is remapped to a different function it needs to
still report the proper interrupt map to the OS instead of assuming
that function number is equivalent to root port number.
This change also includes an update to the PCH function disable
register which was incorrect for CPT/PPT and would cause unpredictable
behavior if used.
The kernel command line was changed to add 'nomsi' in order to force
PCIe devices to use IO-APIC assigned interrupts and not MSI to ensure
that the mapping is correct.
LUMPY current:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.3 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 41518 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 720 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
LUMPY with PCIe port coalesce enabled:
00:1c.0 PCI bridge: Intel Corporation Device 1c10 (rev b5)
00:1c.1 PCI bridge: Intel Corporation Device 1c16 (rev b5)
16: 38988 0 0 0 IO-APIC-fasteoi i915, ahci, ath9k
19: 347 0 0 0 IO-APIC-fasteoi ehci_hcd:usb2, eth0
Change-Id: Ia5f6bb8888b5c38a5dbc88bb25ecdf1fca41ee3e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/978
Tested-by: build bot (Jenkins)
The sata controller comes up in legacy/normal mode and
is currently put into AHCI mode in romstage.
If that is removed and the controller is left alone until the
ramstage driver (like we do on Stumpy/Lumpy) then the resource
allocator will have configured the device for IDE mode with an
IO address in BAR5. Then when the ramstage driver puts the
controller into AHCI mode it will not have the correct resources
to do the rest of the AHCI setup.
So the controller mode needs to be changed in the enable stage
rather than in the init phase. This same register contains
the port map and it is a R/WO (write once) field so the configured
port map must be written at the same time. For non-AHCI mode
the devicetree map was ignored before but it is used now.
Since the port map register is now written at enable step it
does not need to be written again during init.
With this change the sata port map can be reduced to just port 0
and then U-boot does not have to probe all available ports.
Change-Id: I977952cd88797ab4cea79202e832ecbb5c37e0bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/977
Tested-by: build bot (Jenkins)
The OS does not re-execute the APMC 'enable ACPI' SMI
on resume so this has the potential to leave things
in an unknown state.
Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This adds the PCI device id of the LPC controller identifying the
QPRJ/QS stepping of the Panther Point southbridge.
Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/968
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Many PCI devices share the very same driver despite having different
PCI device IDs, which causes a lot of copy and paste of driver
definitions.
This change introduces a way to specify the array of acceptable
device IDs in a single driver entry. As an example the Intel
{Sandy|Ivy} Bridge SATA driver is being modified to use a single
driver structure for all different SATA controller flavors, a few
more Ivy Bridge IDs are being added as well.
BUG=none
TEST=manual
. modified coreboot brought up an Ivy Bridge platform all the
way to Linux login screen.
Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
post_code() was added in our internal tree by duplicating code. It's not of
much use at this point, since the code is quite well tested, so avoid bloating
the bootblock (since compiled with ROMCC).
Also add some missing include files that didn't seem to be needed with an
older version of coreboot.
Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function
naming scheme of the other handlers. Add prototype for mainboard_smi_sleep
(mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge.
Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/933
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
S3.rom is useless for all the other boards which don't use flash to
save sleep/wakeup settings. AGESA-based boards other than persimmon
haven't been validated the S3 resume. They don't need S3.rom yet.
Change-Id: I12693e9556ca6f8e0d80b2ab2dca5c85bdb97685
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/902
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It is for S3, storing the recovring data in the nonvolatile storage,
i.e., flash.
Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/620
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
So far it just setups things right for Bifferboard. We may change it
in the future to fit other hardware.
Change-Id: I1c4ccff4e47b9cb9e31a738f038fc4f4ebe59087
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/808
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Changing CMOS value for power-on-after-power-fail was only honored
after reboot, which is counter intuitive (set from "enable" to "disable",
power-off, replug device -> device turns on; and similar cases).
Change-Id: If1d88c1c34c3333b636ed3ec1e1fb9bea394e615
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/444
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use separate Kconfig option to select a driver directory for
build and the specific type of southbridge to support.
Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Southbridge SP5100 support was compiled with SB700 code, but static
device info structure would use sp5100/chip.h. To solve this drop
support for separate chip sp5100 and adjust the relevant Kconfig
options.
Removes chip directory:
src/southbridge/amd/sp5100/
Rename Kconfig option
from: SOUTHBRIDGE_AMD_SP5100
to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100
Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/679
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)
If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O and
configures the southbridge decode range to what is defined by the
mainboards Kconfig.
Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/632
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If PCI config cycles use MMIO instead of I/O in the SB700
bootblock code the cycles will go nowhere since the MMIO feature
hasn't been configured yet. This change forces the cycles to use
I/O and configures the southbridge decode range to what is specified
by the mainboards Kconfig.
Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/631
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.
Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/630
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/659
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/662
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/663
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/664
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/665
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)
Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The current directory is always part of the search path of cpp when
using #include "..."
Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/648
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
without it, you can't boot from PCI devices like scsi controllers
which require an interrupt set. So preconfigure all pci devices.
Change-Id: I2cd781227701e8363d83bd90e0e36994359fc194
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/603
Tested-by: build bot (Jenkins)
BIOS needs to set the bit mask which ports are iplemented on the
board. Without setting this option, seabios fails to boot from
SATA.
Change-Id: I21de3fde3a9cff7c590226f70fa549274f36e2a8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/601
Tested-by: build bot (Jenkins)
i3100 misses the magic SATA init sequence, which makes all
requests fail. Captured from the vendor BIOS, which writes
those bits on all configurations.
Change-Id: I293b7d9cd681181311ecaced6d7df9b2706c711f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/600
Tested-by: build bot (Jenkins)
We used to put the id section at -0x10, with some boards overriding
this to avoid collisions with romstraps.
Hardcode the location at -0x80, at the possible expense of some space
(0x70 bytes).
This also makes the section easier to find in a binary image.
At some point, CONFIG_ID_SECTION_OFFSET can be removed, so this option
is moved to src/Kconfig.deprecated_options.
Change-Id: I6ce2d6e94e57717939bda070bfe0c9df80ca2a89
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/549
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
