There isn't a history of broken clang compilers yet
so let's give it a chance.
Change-Id: Iddb63700e3850116313c1ddee69111f936191055
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7607
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It's a portable and generic way to halt the system.
Useful when waiting for the platform to reset.
Change-Id: Ie07f3333d294a4d3e982cbc2ab9014c94b39fce0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7605
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Baytrail Gold3 FSP support memory down configuration. Update Minnow Max
to use Gold3 FSP. Set memory down data in devicetree.cb, instead of use
different FSP image.
Change-Id: Ic03da2d2a1cee5144b9a013d3dd9f982ff043123
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7581
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
The in source comment:
/* This function avoids an error on serial console. */
refers to the resource allocator needing to find a non-NULL
function pointer else complaints of "... missing read_resources"
will be spewed.
Unfortunately/fortunately (depending on the time of day) compiler
optimisers have gotten a bit better at optimising away no-op functions
leading to the very message these stubs attempted to avoid. By using
the DEVICE_NOOP formalism that is static inlined 'suggests' (not enforces)
to the compiler to keep these symbols around.
Change-Id: I182019627b6954a4020f9f70e9c829ce3135f63c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7598
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Waiting for (a & 4) == 3 to become true proves futile
unless you're searching for defective hardware or
neutrino impact.
While I'm not 100% sure that this is the actual intent
(no data-sheets at hand, and the public ones are unhelpful
as usual), it's the likely correct version and it's also
boot-tested on intel/d945gclf.
While at it, replace register number with the name found
in the public datasheet.
Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Richland APU A10-5750M
8GB RAM
4MB Flash
Boots to working Linux with SeaBIOS payload. S3 works with
Linux 3.16.3-2 Debian Jessie.
Change-Id: I5d05d1b31400fdb9e41c2e011c5b0bf9986fe970
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/7560
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For the moment we make use of Trinity f15tn AGESA for Richland
f15rl support until we have properly worked out the discrepancies.
Adds RL-A1 Richland stepping cpuid to F15TnLogicalIdTables lookup.
We later wish to merge f15tn and f15rl support into the AGESA in
any case.
Change-Id: Ia9070d4e392ce7eb912771d1c7b3ef1440f8e8a8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7559
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Provide our current development support for Richland. We
would however like to see a unification of 'northbridge/amd/agesa'
instead of another copy-paste merged.
Change-Id: I88005939844d1132cfd3531a9d47389320026814
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7536
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Rather than hunting version across compile tree in board_status,
export it by coreboot itself.
Change-Id: I7f055e6fc077134001ebdb11df7381bbdc71a1fc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6747
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This was copied from P2B-F without doing any modification. It never worked.
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Change-Id: I2c90688c8ff8c3bd272d24f059e8e1bfb86e2b4a
Reviewed-on: http://review.coreboot.org/7555
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
The suggested IRQs 10 and 11 would conflict with PCI IRQ assignment
(10 for most interrupts on this board). Suggest IRQ 6 instead.
It's actually a noop since the code is commented out.
Change-Id: I0fdd8e2091d3dc79cfb1809a9ea5e1e841ca598a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7476
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
.bin is the most convenient format for storing SPDs and since it's
not text format, whitespace check is useless and gives false positives.
Change-Id: I8a7569eac8a1dfbffabe166a38e4dd3e895fdef1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7567
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
According to spec IRQ1 isn't available for PIRQ assignment.
Has gone unnoticed probably because modern OS use MSI or
at least APIC and even with noapic don't use IRQ1 with PCI
IRQs.
Change-Id: Idc7db249007df629b27e8cae41cc80358d5306f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7478
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This is a port of the following:
commit d5c998be99
The coreboot resource allocator doesn't respect resources
claimed in the APIC_CLUSTER. Move the MMCONF resource to the
PCI_DOMAIN to prevent overlap with PCI devices.
Change-Id: I49167dd3f15d0203a7db8950880ab03171d5c170
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7533
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Lets cut down on whitespace differences, fix some typos and indents.
Also make use of ARRAY_SIZE() macro instead of a local redefinition.
Fix NULL pointer checks ordering and not to use zero.
Change-Id: I93f344d300c04570d795659d848255cb1832e1d8
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Not sure what this is about.
Required for BeagleBone (not Black) with HUB in the middle, also
old FX2 senses extra reset if we do this.
Change-Id: I86878f8f570911ed1ed3ec844c232ac91e934072
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3868
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
According to EHCI specification, host controller software stops
the USB Reset condition by writing PORT_RESET=0. Software then
poll-waits this bit until controller hardware has completed USB
Reset sequence and read returns with PORT_RESET==0.
Change-Id: I6033c4d904c2af9eb16f5f3c1eb825776648cc1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3863
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Organized such that it is easy to support devices that do not
export special Debug Descriptor. Some of these can still work
in a fixed configuration and/or require additional initialisation
for UART clocks etc.
Change-Id: Id07fd6b69007332d67d9e9a456f58fdbca1999cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7209
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
