Some of the boards use the EC_SYNC pin to wake the AP but do not
advertise the pin as wake capable in the CREC _CRS resource. Relevant
boards were determined through empirical testing and inspection of gpio
configuration.
Update the ACPI tables for rex, brya, and brox based boards to advertise
their EC_SYNC pin as wake capable.
BUG=b:243700486
TEST=-Dump ACPI and verify ExclusiveAndWake share type is set when
EC_SYNC_IRQ_WAKE_CAPABLE is defined
-Wake Aviko via keypress and verify chromeos-ec as wake source
-Wake Screebo via lid open and verify chromeos-ec as wake source
Change-Id: I5828be7c9420cab6ae838272c8301c302a3e078c
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79374
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even
though they're unused at the moment, but those might still be useful to
keep around, since the SATA controller can have different PCI device IDs
depending on in which mode it is in.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
These IDs are not used as crashlog data is not stored in CBMEM now.
(Ref CL: I43bb61485b77d786647900ca284b7f492f412aee
Title: soc/intel/common,mtl: Refactor BERT generation flow for crashlog)
BUG=b:298234592
TEST=Able to build REX.
Change-Id: Ie38571dece89a995d582099d34f0a1dd57cb936f
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
With earlier flow, a chunk of CBMEM region was allocated for each SRAM
e.g., PUNIT SRAM, SOC PMC SRAM and IOE PMC SRAM. Then entire SRAM
content was copied to dedicated CBMEM region. Later in acpi_bert.c, the
BERT table was getting created for each chunk of CBMEM. This flow was
not considering creating separate entries for each region of crashlog
records. It resulted in only the first entry getting decoded from each
SRAM.
New flow aims to fix this issue. With new flow, a simple singly linked
list is created to store each region of crashlog records from all
SRAMs. The crashlog data is not copied to CBMEM. The nodes are
allocated dynamically and then copied to ACPI BERT table and then
freed. This flow also makes the overall crashlog code much simpler.
BUG=b:298234592
TEST=With this change decoding crashlog show comprehensive details,
tested on REX.
Change-Id: I43bb61485b77d786647900ca284b7f492f412aee
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78257
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The optimization of sleep time in acpi code includes reducing the sleep
duration and increasing the polling frequency within the acpi _ON/_OFF
method. StorageD3Enable is activated in Google/Rex, and this
optimization results in a saving of approximately 25ms in D3cold resume
time, reducing it from around 160ms to 135ms.
BUG=b:296206467
BRANCH=firmware-rex-15709.B
TEST=boot test verified on google/rex
verified _ON/_OFF Method in SSDT.
verifid kernel log in s0ix test -
0000:00:06.0: PM: pci_pm_resume_noirq
Change-Id: I7ba960cb78b42ff0108a48f00206b6df0c78ce7a
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Enable Acoustic noise mitigation for google/screebo and set slew rate
to 1/8 for IA domain and ignore the slew rate for SA domain.
BUG=b:312405633,
TEST=Able to build and boot google/screebo.
Before:
[SPEW ] AcousticNoiseMitigation : 0x0
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x0
[SPEW ] SlowSlewRate for Index = 0 : 0x0
After:
[SPEW ] AcousticNoiseMitigation : 0x1
[SPEW ] FastPkgCRampDisable for Index = 0 : 0x1
[SPEW ] SlowSlewRate for Index = 0 : 0x2
Change-Id: Ib86939ab48c2c6e7d0491d7c1cb4a2c7c6a1b568
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79323
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Acoustic noise in PCBs is a common problem and be caused by a variety
of factors, including:
Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal
expansion.
This patch adds the UPDs to FSPM header file for mitigating the acoustic
noise.
FSPM:
1. AcousticNoiseMitigation
2. FastPkgCRampDisable
3. SlowSlewRate
BUG=b:312405633
TEST=Able to build and boot google/rex.
Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
As we look at unifying the format of coreboot code (/src, excluding
src/vendorcode), we need a code-beautifier configuration that works
well with the coreboot style. This patch is an attempt to match the
existing code styles as much as possible.
There are going to be some trade-offs in any code formatter. Tables
which have been hand-formatted probably won't look as good. These
can be specifically marked to be excluded from the formatter, however
this should be the exception, not the rule.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I70341d77e167c145f447594b6b0bef628cea83c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78832
Reviewed-by: Zebreus <lennarteichhorn@googlemail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCH identification functions and `pch_iobp_update` are used in multiple
stages. Move them out of `pch.c` to drop some ugly preprocessor usage.
Subsequent commits will use `pch_iobp_update` in romstage as well.
Change-Id: I8d33338a4f74fd03c8f99f8fcece99b63c28adab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79624
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option is nowhere selected and there is only a single case left
where it's used. Guarding the check in pci_rom_load() seems like a
bad idea: As the code would be copying all VGA ROMs to the same
location, it would be only working by chance (if the last encoun-
tered ROM is the right one). Hence, drop the guard and always check
for the correct device.
Change-Id: Ib283bf0a65367b99099a3bfcbd27585d44235eb9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79596
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's neither need to remove get_hw_mem_hole_info from the code if the
Kconfig option was set to 0 nor the actual value didn't make any
difference in the behavior of the code: When node_id has still its
initial value of -1, domain_read_resources won't use the value of
hole_startk, and when node_id is set to 0, get_hw_mem_hole_info also
sets hole_startk to the actual value that then gets used by
domain_read_resources.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieffab695a3151ed7f6bf9d6c880bbb43eecf7893
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79609
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node, so the nodeid parameter of
get_node_pci is always 0. Since this SoC has a chipset devicetree, we
can just use DEV_PTR(ht_X) instead of the pcidev_on_root call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bf9d214b4c2e5d995976fb79fef6fe43a6e9fa0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79608
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node and since we're in ramstage when
domain_read_resources gets called, there's DRAM on this node, so no need
to check for this. To be extra sure, also initialize basek and limitk
before calling get_dram_base_limit with pointers to those as arguments.
This won't be necessary for the code to work as intended, but will
probably keep the compiler from complaining. Also move the declaration
of basek, limitk and sizek to the beginning of the function.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4ef8011eb57b16218b8f5fea295900b855c3014b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79611
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node and also only has one DRAM controller,
so there is only one valid DRAM base and limit register. It's also worth
mentioning that the assumption made in get_dram_base_limit that the n-th
node is using the n-tn DRAM range register was valid for K8, but not
necessarily on newer generations than that.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0529c66e8d0e6c8eb42eec2c6d9d2e892287865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79607
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This APU is always a single-node and also only has one DRAM controller,
so we don't need to loop over the different nodes to find the memory
hole below 4GB. We also don't need to check for the special case where
the memory hole is non-DRAM address space between the parts of the
address space decoded by different DRAM controllers.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9793d911d2d496be49168c06d83ceb802bc2b647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This APU is always a single-node, so domain_read_resources only needs to
handle exactly one node and doesn't need to loop over the nodes.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4218077cb4e11b762ce0e8694a97bdec33eaa056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This SoC only supports a single-node configuration, so all the code
related to multi-node support can be removed. In this commit only the
get_fx_devs function and related code are removed for better
reviewability. In f1_write_config32 it's no longer needed to loop over
the different devices of the different nodes, so only a single PCI
config space write remains.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dc7324d3fcd0d07ac7a3a246a740fd9e91c3840
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79604
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This APU is always a single-node system and bits 4..6 of the node ID
register D18F0x60 are also marked as reserved in BKDG #52740 Rev 3.05.
On an APU2 board with quad-core APU, this register reads back 0x00030000
which results in a value of 1 to be returned from get_node_nums, so this
patch doesn't change behavior, but stops using reserved bits.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65ed1124c0ca8e7eba54ff53dc626d35cd5e2e58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79603
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This system only has one northbridge and amd_initcpuio has already set
up the routing of the legacy VGA IO and MMIO ranges to it. Since only
the pci_dev_set_resources call remains in nb_set_resources, use
pci_dev_set_resources directly as set_resources function.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib3835db9fd83221ac2b8e34d998f938812d24413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since the IOMMU is always function 2 of device 0 on bus 0, the device
operations can be statically assigned in the devicetree and there's no
need to bind the IOMMU device operations to the PCI device during
runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84e949500ee86e0fcb2d15791502f5e3e7127703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since the northbridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the northbridge device operations to the PCI
device during runtime via a list of PCI IDs.
TEST=PC Engines APU2 still boots and doesn't show any new problems
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia7faaa468ff77e05c378c5555622c3584cfe3f81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.
TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This patch provides a way to mask the 3-strike error on Intel
Meteor Lake SoC platform across pre-prod and prod SoC.
This patch decouples MSR selection for 3-strike error disablement, ensuring compatibility across SoC types.
Without the correct MSR been programmed the SoC platform is unable to disable 3-strike error.
BUG=b:314883362
TEST=Disable the 3-strike on google/screebo with QS silicon.
Change-Id: I5363102deea67c44c9433a3f66c92badb0d0f182
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79473
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When caching the ramstage for suspend/resume, we copy the entire image
as it resides in RAM. The last part of that, CONFIG_HEAP_SIZE bytes, is
the heap that will be reinitialized when the ramstage is started again.
As such, copying doesn't make sense and complicates HEAP_SIZE
configuration (because it needs to fit the space-constrained cache
location) and costs time and space. Therefore, skip the heap.
Side notes:
- When building with ASAN, program.ld indicates that it will allocate
some more space after the heap. This is not a problem, we just copy
an ASAN-sized copy of the heap.
- Heap use is managed in src/lib/malloc with statically allocated
variables. Because ramstage is cached before it's executed, these
values will be reset to their compile-time default values, too.
Change-Id: I6553dc8b758196f2476af2e692c0421d0fa2b98e
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79525
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The end-of-build targets weren't very granular previously, so warnings
could be lost instead of being printed at the end of the build.
This separates the end-of-build targets into 4 different groups, in this
order:
- build_complete: The coreboot build itself is done
- files_added: All files have been added to CBFS
- show_coreboot: Display any normal coreboot build messages
- show_notices: Display any warnings or notes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia67446f164b8e66415a1a8c196999316fdf39f1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79382
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
