The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Many (if not all) platforms have moved to using consistent
boot flow constructs where a weak car_stage_entry() is no longer
necessary to avoid the complexity of handling the numerous and
different boot flow combinations. The weak symbol is just causing
issues so remove it.
Change-Id: I7e7897c0609aac8eef96a08bb789374b2403956d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35135
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MSRs were already named as PRMRR in broadwell, just
mismatching with the rest of the code. All later devices
use the names PRMRR and UNCORE_PRMRR for these MSRs.
Reflect the name change in structures and local variables.
Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.
BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.
Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.
Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.
Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.
BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system
Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, we don't have UPDs to set emmc settings per mainboard on CML.
This code change is to create mmc.c to provide interface to override dll
settings per mainboard.
Notice: set_mmc_dll function will override the dll values in FSP.
BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.
Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Move descriptions below the license header
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51d5b1f01ff47ed752761116e3f32cb9e168584f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34637
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As discussed on the mailing list and voted upon, the coreboot project
is going to move the majority of copyrights out of the headers and into
an AUTHORS file. This will happen a bit at a time, as we'll be unifying
license headers at the same time.
Additional changes in this patch:
- Remove comments saying that a file is based on another file from the
coreboot project.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If61689db67c58f0d66ab96ca749bfcd589935ce2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a new Kconfig symbol that allows an x86 device to begin execution
when its reset vector is in DRAM and not at the traditional 0xfffffff0.
The implementation will follow later, this is just to setup various
ENV_xxx definitions correctly for the build environment.
Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This enables the use of .bss section for ENV_BOOTBLOCK
and ENV_VERSTAGE even with CAR_GLOBAL_MIGRATION=y.
In practice, boards with CAR_GLOBAL_MIGRATION=y currently
build with romcc-bootblock so they will not be using .bss.
Change-Id: Ie9dc14f3e528d3e4f48304f4d7de50df448a8af6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This allows for minor optimization as num_timestamps becomes
a constant zero for a function with local scope. The loop
with calls to timestamp_add() gets removed from bootblock.
Change-Id: Id230075c0e76fe377b6ea8c8ddf8318e07d29b91
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ENV_ROMSTAGE_OR_BEFORE is a direct replacement for testing
defined(__PRE_RAM__) as a true statement instead of with the
help of the preprocessor.
Note that for x86, due to existence of ENV_POSTCAR and ENV_SMM,
ENV_ROMSTAGE_OR_BEFORE and ENV_RAMSTAGE are not the inverse of
each other.
Change-Id: Ibd2292f922ccb9e79d10ca9bc35797048d174287
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34939
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
