This change adds support for variant_memory_sku() that allows variant
to return memory SKU ID. Current implementation of memory_sku() is
renamed to weak implementation of variant_memory_sku(). Functionally
this change should be the same as before for all hatch variants. This
function will be overriden by helios in a follow-up CL.
BUG=b:133455595
Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
The limitation for SD-Card was originally only made for mc_apl2
mainboard. Since other mc_apl mainboards also use the SD-Card interface,
the speed mode setting is made in the parent mainboard_final.
In additional, all UHS-I bus speed modes are disabled because of a
limitation for industry use cases. This means that only HS mode is
permitted.
Change-Id: I2f1b51f13a53c2507c52d6a169d6384b8570b3bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch makes VGPIO_3 GPIO PIN output and low independent of
cnvi is connected or not.
BUG=b:123062346
BRANCH=None
TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low.
Change-Id: I629b99676f56747de1b244724709e14069250097
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taken from
"Intel 6 Series Chipset and Intel C200 Series Chipset"
Document Number: 324645-006 and
"Intel 5 Series Chipset and Intel 3400 Series Chipset"
Document Number: 322169-004 and
"Intel 6 Series Chipset"
Document Number: 324645-001.
UPDCR was found in GNU/Linux's drivers/pci/quirks.c.
DMC2 was guessed as it's close to DMC and defined for 5 series chipset.
Test:
Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences.
Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This CL allows that everyone can use main() in lib/bootblock.c
even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main
functions used in some soc/ to avoid the collision with the
main function defined at lib/bootblock.c.
Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GCFC (Graphics Clock Frequency Control) read is not used at
the line below.
As the default value is zero, let's remove unused read.
Found-by: scan-build 7.0.1-8
Change-Id: I82c567e3a5b0c0c4a8596ea0cb7693667c71b720
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The code currently checks that 4 <= dev_index <= 10, which after
subtraction by 4 can index into an array of length at most 7. This is
fine for the largest cpl array (which does have length 7), but is
too large for some of the others, which are smaller. This adds bounds
checks for each array access to ensure they are all within bounds.
Change-Id: I1610d35ca6cbb6cfb42c251e75b0e8b22b64252b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229676
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The speed argument should be one of the six values from the mem_clock
enum, so something is very wrong if this is not the case. Better to
die now than return 0, which will cause a division-by-zero error
later on where this function is called. The first two speeds are also
unsupported and have the same problem with returning 0, so die on those
as well.
Change-Id: Ib628c0eed3d6571bdde1df27ae213ca0691ec256
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1391088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33409
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the decoded SPD DRAM frequency is slower than the controller minimum,
then there will be an unsigned integer underflow in the following loop,
which will lead to a very large out of bounds array access. Ensure this
does not happen.
Change-Id: Ic8ed1293adfe0866781bd638323977abd110777e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1229675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Judging from the state machine on page 281 of the Rockchip RK3288
Technical Reference Manual (Rev 1.0 - Jun 2015), the fall through
from the INIT_MEM -> CONF states is intentional, since that is the
only way to get to the ACCESS state. Add a comment to explain this.
Change-Id: I1d0cfea07211c54d6a906f5a7481c2c760f8ef0d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1291959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
There are two hard things in computer science: cache invalidation,
naming things, and off-by-one errors. -- Anonymous
var_num records the number of initialized entries in the reg_var array.
However, this means the index of the last initialized element is one
less than the value of var_num, so we need to take that into account
when indexing into the array. This has already been fixed in several
other places (eg. sb/amd/pi/hudson/lpc.c), so let's also do so here.
Change-Id: Ibefabaca42866a3f2b22eff979c73badf86ac317
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The FSP_CAR option has additional configuration options whose default
values result in boot failures. Since default values should always boot,
default to the open-source CAR NEM Enhanced implementation instead. This
also allows us to get rid of an unnecessary vendor-specific special case.
Change-Id: I30b1808f91701c07dce6f1de08c213150e8a675a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34287
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SOR_LINK_SPEED_G5_4 is unsupported, but it is not invalid, so it
suffices to return here instead of printing the next warning message.
Change-Id: Ifca3c52635e9a39af42e6616821d1099c43c237c
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1293137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
last_unitid is immediately overwritten in the do loop, so this assignment
is not needed. This a relic from old code that commit 13f1c2af8b made
obsolete, but was never removed.
Change-Id: I2eecddd025f7a64b0a70fc07a61ebb43aba757d6
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add generic WiFi driver to support common device operations across
multiple types of WiFi controller.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the SSDT table contains SAR tables
and wakeup GPE information. Ensure that the SSDT table is same after the
change.
Change-Id: Ica5edf95a37c8ed60f7e159d94fd58af5d41c0ef
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
