sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
39,960 Commits 47 Branches 30 Tags
ee25a6fb0e4bd2e43ce2e120c83b609e1aff32b6
Commit Graph

39960 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Raul E Rangel
f38dc8b11d mb/google/zork: Fix duplicate i2c_tunnel uid 
This conflicts with the MSTH i2c_tunnel.

BUG=b:175146875
BRANCH=zork
TEST=Boot trembyle and inspect ACPI tables.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-25 08:53:02 +00:00
Raul E Rangel
c39f009739 soc/amd/picasso/acpi: Add UID for PCI INT devices 
If a _HID/_CID are not unique, we need to add a _UID field to
differentiate the objects.

BUG=b:175146875
BRANCH=zork
TEST=Boot linux, dump ACPI table and verify UIDs are unique

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2021-01-25 08:52:53 +00:00
Martin Roth
c6c64e844b util/crossgcc: Remove obsolete dockerfile 
This file was added here before util/docker existed.  Anyone using this
dockerfile should use the coreboot-sdk docker container instead.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7114abc9c91ba2d6fcfef80ae6e7d1a7a3d253cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-01-25 08:52:24 +00:00
Tim Wawrzynczak
2e3edcfbe0 mb/google/volteer/eldrid: Use #define symbols for usb2_ports config 
It's easier to understand what these symbolic names mean rather than
using the constants; the static.c will will end up (indirectly)
including `soc/usb.h` therefore the macros are in scope here.

Change-Id: I5ef977a05a2522e177f32c99bfab74f9288ae869
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2021-01-25 08:52:01 +00:00
Kevin Chiu
845b65bf5e mb/google/zork: update USB 2.0 controller Lane Parameter for gumboz 
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3

BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass USB 2.0 SI eye diagram verification

Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
 2021-01-25 08:51:26 +00:00
Kevin Chiu
5a27b75642 mb/google/zork: update USB 2.0 controller Lane Parameter for dirinboz 
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3

BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. pass USB 2.0 SI eye diagram verification

Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
 2021-01-25 08:51:21 +00:00
Angel Pons
cbde6410a0 mb/google/kahlee: Deduplicate now-equivalent mainboard.c 
The only difference is an additional include that is no longer needed.

Change-Id: I0053d03aa4d05f5c0fa833d8634419b6667e38a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49832
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 08:50:34 +00:00
Angel Pons
e4abe7fd5a bayhub bh720: Configure VIH tuning via devicetree 
There's no need to repeat the same code on every board.

Change-Id: I2e19decfe8609fa644e609673a56ee5109bafefa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49831
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 08:50:17 +00:00
Furquan Shaikh
f06d046c10 soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver 
This change uses the newly added meminit block driver and updates TGL
SoC and mainboard code accordingly.

TEST=Verified that UPDs are configured correctly with and without this
change.

Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
 2021-01-25 08:48:57 +00:00
Furquan Shaikh
859ca18ced soc/intel/common: Add support for populating meminit data 
This change adds support for a common block memory driver that can be
used for performing the required operations to read SPD data for
different memory channel DIMMs. This data can then be used by the SoC
code to populate different memory related UPDs.

Most recent Intel platforms follow a similar pattern for configuring
FSP-M UPDs for initializing memory. These platforms use one of the
following topologies:
1. Memory down
2. DIMM modules
3. Mixed

Thus, SPD data is either obtained from CBFS (for memory down topology)
or from on-module EEPROM (for DIMM modules). This SPD data read from
CBFS or EEPROM is then passed into FSP-M using SPD UPDs for different
channels/DIMMs as per the memory organization.

Similarly, DQ/DQS configuration is accepted from mainboard and passed
into FSP-M using UPDs as per the FSP-M/MRC organization of memory
channels.

Different memory technologies on a platform support physical channels
of different widths. Since the data bus width is fixed for a platform,
the number of physical channels is determined by data bus width /
physical channel width. The number of physical channels are different
depending upon the size of physical channel supported by the memory
technology. FSP-M for a platform uses the same set of UPDs for
different memory technologies and aims at providing maximum
flexibility. Thus, the platform code needs to format mainboard inputs
for DQ, DQS and SPD into the UPDs appropriately as per the memory
technology used by the board.

Example: DDR4 on TGL supports 2 physical channels each 64-bit
wide. However, FSP-M UPDs assume channels 16-bit wide. Thus, FSP-M
provides 16 UPDs for SPDs (considering 2 DIMMs per channel and 8
channels with each channel 16-bit wide). Hence, for DDR4, only the SPD
UPDs for MRC channel 0 and 4 are supposed to be used.

This common driver allows the SoC to define the attributes of the
platform:
1. DIMMS_PER_CHANNEL: Maximum DIMMs that are supported per channel by
any memory technology on the platform
2. DATA_BUS_WIDTH: Width of the data bus.
3. MRC_CHANNEL_WIDTH: Width of the channel as used by the MRC to
define UPDs.

In addition to this, the SoC can define different attributes of each
memory technology supported by the platform using `struct
soc_mem_cfg`:
1. Number of physical channels
2. Physical channel to MRC channel mapping
3. Masks for memory down topologies

Using the above information about different memory technologies
supported by the platform and the mainboard configuration for SPD,
the common block memory driver reads SPD data and provides pointers to
this data for each dimm within each channel back to the SoC code. SoC
code can then use this information to configure FSP-M UPDs
accordingly. In addition to that, the common block driver also returns
information about how the channels are populated so that the SoC code
can use this information to expose DQ/DQS information in FSP-M UPDs.

This driver aims at minimizing the effort required for supporting
different memory technologies on any new Intel SoC by reducing per-SoC
effort to a table of configurations rather than having to implement
similar logic for each SoC.

BUG=b:172978729

Change-Id: I256747f0ffc49fb326cd8bc54a6a7b493af139c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49040
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-25 08:48:38 +00:00
Bora Guvendik
99157c1f4a soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD 
Make IGD disable when mainboard user selects SOC_INTEL_DISABLE_IGD.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib297b339ce15ccb9212da32b27022610bc8aa2b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2021-01-25 08:48:24 +00:00
Elyes HAOUAS
61ab526971 mb/asus/p5ql-em/Kconfig: Drop 'select ARCH_X86' 
ARCH_X86 is already selected.

Change-Id: I2be69e0b7a1889794121ed94380e543ac420218b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-25 08:47:08 +00:00
Angel Pons
21f9650b7f soc/intel/broadwell: Improve LPD0/LPD3 SerialIO ACPI methods 
Creating named objects within a method is highly inefficient. So, pass a
reference to the OperationRegion field that needs to be updated instead.

Change-Id: I88272fc5cbe35427ccb5fc50789d47b66ace88fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-01-24 23:26:05 +00:00
Angel Pons
9f0093d208 cpu/intel/model_2065x: Drop configurable TDP copy-pasta 
Configurable TDP is only supported by Ivy Bridge onwards.

Change-Id: I8a742ab6d9d22b325ed725df4f749955efb3028f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-24 23:23:43 +00:00
Angel Pons
00d66603db cpu/intel/model_2065x: Drop unused c-state code 
None of the mainboards have the magic SpeedStep device, so the C-state
generation function bails out without doing anything. Moreover, this
code is broken and was copied from Sandy Bridge. Thus, drop it.

Change-Id: I580157ee33c599af5fc48b06eeb39cb32c9831ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-24 23:23:35 +00:00
Angel Pons
ae4eba9be5 soc/intel/broadwell: Drop enable check from LPD0/LPD3 
When SerialIO devices are disabled, their _STA method evaluates to 0,
which means the device is not present. It is expected that OSPM would
not attempt to change the power state of a device that is not present.
Lynxpoint does not have these checks, thus remove them from Broadwell.
Also remove the now-unused Arg1 parameter to avoid warnings from IASL.

Change-Id: Ic5e999ac1171ce49db66bec45c58d8aa5711ec53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 23:23:24 +00:00
Angel Pons
0ec903a73b Doc/mb/lenovo/Sandy_Bridge_series.md: Clarify installation 
Unlike Ivy Bridge series, there isn't a method to flash coreboot
internally when running vendor firmware (yet). Until someone finds a way
to bypass flash protections, the first flash has to be done externally.

Change-Id: Idaff264f2b7277516d69d1323f1a0c885b28c3db
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2021-01-24 23:21:23 +00:00
Angel Pons
76943a3443 Doc/mb/lenovo: Correct typo 
Change-Id: If31c59f21c5533d8b5b015c9e60edd6e4e7072e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49847
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-24 23:21:17 +00:00
Elyes HAOUAS
37158c588e mb/google/poppy: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: I4f8b77b3f196ca51346bb7932a40875c4dd5d2a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:53:35 +00:00
Elyes HAOUAS
2a08ca7e7a ec/google/wilco: Convert to ASL 2.0 syntax 
Change-Id: Ie5c88f8acee16ff77f9707d7ed56436bf0d521b1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:51:39 +00:00
Elyes HAOUAS
5b880a1333 ec/compal: Convert to ASL 2.0 syntax 
Change-Id: I934f9d1664f657597f15daed2d2d0c41cd124d21
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:50:30 +00:00
Elyes HAOUAS
fafd512842 ec/acpi: Convert 'ec.asl' to ASL 2.0 syntax 
Change-Id: Ifd85d2eabbda4e25406f20391489c0e7ad314348
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:49:06 +00:00
Elyes HAOUAS
b06dea9e90 mb/razer: Convert to ASL 2.0 syntax 
Generated build/dsdt.dsl are same.

Change-Id: I9c7cbc4ee874657a7381b1b220872c4ebecd0821
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46085
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-24 21:48:06 +00:00
Elyes HAOUAS
488f5d8593 mb/packardbell: Convert to ASL 2.0 syntax 
Built for packardbell/ms2290 provides same build/dsdt.dsl file.

Change-Id: I5f1dbb2595c3ee8cb35bb8a6431288f4a96ce978
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:47:40 +00:00
Elyes HAOUAS
a59b5f8ca3 mb/lippert: Convert to ASL 2.0 syntax 
Built provides same dsdt.dsl file for  lippert/frontrunner-af

Change-Id: I61d8af98e2003547e332f463b23c1e1cf79f7f00
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:46:27 +00:00
Elyes HAOUAS
f6676df8b5 mb/lenovo/x230: Convert to ASL 2.0 syntax 
Change-Id: I18667ae74454e0db83fb40d8f130909510ddc379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:45:06 +00:00
Elyes HAOUAS
8972cacd48 mb/lenovo/x1_carbon_gen1: Convert to ASL 2.0 syntax 
Change-Id: I9764d90e713f35d54056fbafae3e3ada18bea1eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:44:51 +00:00
Elyes HAOUAS
bbc3cf499a mb/lenovo/x131e: Convert to ASL 2.0 syntax 
Change-Id: I3bee00030f03577b0449202233f7e76f7de96339
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:44:27 +00:00
Elyes HAOUAS
f608a9b8c6 mb/lenovo/t530: Convert to ASL 2.0 syntax 
Change-Id: I95eab372b3c6b6df5231f0d232e878576bab5290
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:44:09 +00:00
Elyes HAOUAS
03437f0773 mb/lenovo/t520: Convert to ASL 2.0 syntax 
Change-Id: Ice7cfc263c339ba9ec3705c1cee44a6d69f2e4d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:43:55 +00:00
Elyes HAOUAS
15a5b0a571 mb/lenovo/t440p: Convert to ASL 2.0 syntax 
Change-Id: I91e25fe62080582b925fa1f1a88512f318ab9415
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:43:42 +00:00
Elyes HAOUAS
3b2d9970dc mb/lenovo/t430s: Convert to ASL 2.0 syntax 
Change-Id: I2825dff6b68da9b1e2bb13f03a4251af02438b66
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:43:23 +00:00
Elyes HAOUAS
c0ee13a730 mb/lenovo/t430: Convert to ASL 2.0 syntax 
Change-Id: Id4a724193c4c120373a3e696ebd1fb7155fd8531
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:43:04 +00:00
Elyes HAOUAS
9d403afe5b mb/lenovo/t420s: Convert to ASL 2.0 syntax 
Change-Id: I6e928c23165abad623ee3c2a26e090b029d55572
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:42:48 +00:00
Elyes HAOUAS
1cc58cff6b mb/lenovo/l520: Convert to ASL 2.0 syntax 
Change-Id: I9d0e4982888823bb62a174a603a126676e68e308
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:42:32 +00:00
Elyes HAOUAS
dc324792be mb/lenovo/g505s: Convert to ASL 2.0 syntax 
Change-Id: I56f844706ba6bde3e57a6a81ff1d8e16863913f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:42:17 +00:00
Elyes HAOUAS
9dfa63b3fd mb/lenovo/t420: Convert to ASL 2.0 syntax 
Change-Id: I3890f75e3c27a689e9d57b4708514160e1550fdb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:41:18 +00:00
Elyes HAOUAS
cb108eef21 mb/lenovo/t410: Convert to ASL 2.0 syntax 
Change-Id: I5859c64b0ccd1dfdce040b2c3bbdd9192617ffbe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:41:03 +00:00
Elyes HAOUAS
9759dc334e mb/lenovo/x60: Convert *.asl to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: I305561625d973093645236c77ef13a96ab780f94
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:40:25 +00:00
Elyes HAOUAS
328a023795 mb/lenovo/x220: Convert to ASL 2.0 syntax 
Change-Id: I4c5c67d70e004eeece61e66d427d6f9df9cab4ec
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:39:37 +00:00
Elyes HAOUAS
23af35f040 mb/lenovo/x201: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' files are identical.

Change-Id: I3b553e1b68ee8f236fcab311a076001b94a47975
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46204
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-01-24 21:39:18 +00:00
Elyes HAOUAS
965f98c8dc mb/lenovo/x200: Convert to ASL 2.0 syntax 
Generated 'build/dsdt.dsl' are identical.

Change-Id: I0767afcb0ffdd6f9a8d83209955d42d9e89325e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:38:12 +00:00
Elyes HAOUAS
635ac11deb mb/biostar/am1ml: Convert to ASL 2.0 syntax 
Generated 'dsdt.dsl' files are identical.

Change-Id: Ifdd5008bcb9c7e41e637a30f70316c7926f927b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:36:28 +00:00
Elyes HAOUAS
d67cf181bf soc/intel/quark/gpio_i2c.c: Use __func__ 
Change-Id: Id84a88933d32f60dd8d864d9a10d84a2b3c365ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:28:19 +00:00
Elyes HAOUAS
7dbc4a4658 soc/intel/denverton_ns/pmc.c: Use __func__ 
Change-Id: I06134e48b2d33c178883fc2047bcfbad417c6d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:27:07 +00:00
Elyes HAOUAS
f9e18520c9 soc/intel/denverton_ns/npk.c: Use __func__ 
Change-Id: Ib0f425d74bc219ef518394526b51f2756eb95d61
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2021-01-24 21:26:23 +00:00
Elyes HAOUAS
e98dbf31f2 soc/intel/denverton_ns/lpc.c: Use __func__ 
Change-Id: Ic83a6a5db3b3d8a08c92064f8039d1bac825ffc3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:25:56 +00:00
Elyes HAOUAS
9cf49da224 mainboard/lenovo/s230u/smihandler.c: Use __func__ 
Change-Id: If46ef5ffbd3de82d793a095b011e5740b776ff14
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:24:28 +00:00
Elyes HAOUAS
e167c38775 mainboard/intel/strago/ec.c: Use __func__ 
Change-Id: Ifa30e9d2a71eae9a438e84367fd8b4f8bd920983
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:24:05 +00:00
Elyes HAOUAS
038dc4535c mainboard/intel/emeraldlake2/ec.c: Use __func__ 
Change-Id: I75f534245d37f401357b611efc5c190e8a872d02
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-01-24 21:23:44 +00:00