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Author SHA1 Message Date
JingleHsuWiwynn
20fa59fc2c arch/x86/smbios: Let SMBIOS type 9 be able to write slot ID 
The slot ID can be passed in from the function caller but
parsing slot ID from devicetree is not yet supported and
would still be 0.

Add Slot ID in SMBIOS type 9 for Delta Lake.

Tested=Execute "dmidecode -t 9" to verify.

Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-04-22 12:42:46 +00:00
Felix Singer
efa5a46350 soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512 
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore,
default to 512 in the SoC Kconfig and drop it from related mainboard
Kconfigs.

Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-22 10:23:30 +00:00
John Zhao
091532d8ee ACPI: Fix the devices scope in the SATC structure 
This change adds the ATC_REQUIRED flag for the address translation cache
indicator and fixes the devices scope entry in the SATC reporting
structure. The SoC integrated devices in the specified PCI segment
with address translation caches are a type of PCI Endpoint Device.

BUG=None
TEST=Built image successfully.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I57b3551f11502da48f3951da59d9426df5a40723
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Nico Huber <nico.h@gmx.de>
 2021-04-22 10:15:11 +00:00
Shelley Chen
f095d15d0e soc/qualcomm/sc7280: Modify Makefile to use sc7280 blob 
Now that qc_sec has landed for sc7280
(https://review.coreboot.org/c/qc_blobs/+/51941), we can start using
it instead of the sc7180 placeholders.

BUG=b:182963902
BRANCH=None
TEST=emerge-herobrine coreboot

Change-Id: I5d1014287238d383ef6cd186888845eba0f69750
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2021-04-21 23:09:30 +00:00
Shelley Chen
ecc720b261 3rdparty/qc_blobs: Uprev to new HEAD (02ba9a6) 
Change-Id: I18fc6443a6972e22c979daaf68d0b9c046d1866f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
 2021-04-21 23:09:22 +00:00
Raul E Rangel
c7048323f4 acpi: Add acpigen_write_LPI_package 
Low Power Idle States defines additional information not present in the
_CST.

See ACPI Specification, Version 6.3 Section 8.4.4.3 _LPI.

BUG=b:178728116, b:185787242
TEST=Boot guybrush and dump ACPI tables

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I4f5301b95ff8245facaf48e2fbd51cc82df2d8cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-04-21 22:27:55 +00:00
Raul E Rangel
a89a4ea8ea soc/amd/{cezanne,common}/acpi: Add _OSC method 
The linux kernel requires a valid _OSC method. Otherwise the _LPI table
is ignored.
See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/acpi/bus.c;l=324

Before this patch:
acpi_processor_get_lpi_info: LPI is not supported

After this patch:
acpi_processor_evaluate_lpi: ACPI: \_SB_.CP00: ACPI: Found 4 power states

BUG=b:178728116
TEST=Boot OS and verify _LPI table is parsed

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44e554b9db6f70fdd1559105cdaee53aeb2bfbf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-04-21 22:27:39 +00:00
Raul E Rangel
e3f7645a8b acpi: Add acpi_osc.h 
See ACPI Specification, Version 6.3, Section 6.2.11 _OSC (Operating
System Capabilities)

We can add more UUIDs and capability flags in the future.

BUG=b:178728116
TEST=Builds

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6e2ac1e1b47b284489932d6ed12db9d94e8d7310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2021-04-21 22:25:36 +00:00
Felix Held
d3be9ba902 soc/amd/cezanne: add SMU settings to devicetree 
BUG=b:182297189
TEST=none

Cq-Depend: chrome-internal:3772425
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifbcc85cc10d59f1418bbf0ed4a0dc7549d589a26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-04-21 22:13:30 +00:00
Felix Held
5dea8271b6 soc/amd/picasso/chip.h: improve comments on downcore_mode 
Clarify that the downcoring is about deactivating physical cores.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8a9d1cedff995c507c3be72e7665953e1659238
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52554
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 22:12:36 +00:00
Felix Held
b5c2350145 soc/amd/picasso/chip.h: use boolean type for smt_disable 
Even though the UPD field this information is finally written to is an 8
bit value, the smt_disable option is only a boolean.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaac49944993a28ffb98a80201effe1238ec60875
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52553
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 22:12:28 +00:00
Felix Held
7890380266 soc/amd/picasso/chip.h: use types.h 
Since the next patch will use a boolean, replace the stddef.h and
stdint.h includes with types.h to have all that we'll need.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0d062c8de29aa3688a911d7887faf592020b33c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52552
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 22:12:14 +00:00
Felix Held
d0b5164cd0 soc/amd/cezanne: add downcoring and SMT disable settings to devicetree 
BUG=b:184162768
TEST=none

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id03454ed2be242bce9497560c089f75046ed7e32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52197
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 22:12:06 +00:00
Felix Held
02bfbf4430 soc/amd/cezanne/chip.h: include missing types.h 
Since we use uintX_t, bool and friends, we need to make sure to include
the corresponding definitions.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icb8a6e93d7f1923ac95e584fb3e33c391963f5ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52551
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 22:11:53 +00:00
Bill XIE
a060e3ce5c mb/asus/p8z77-v_lx2: Add CMOS option support 
Based on asus/p8z77-m_pro's, with NMI set to disabled by default, and
all available gfx_uma_size values.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I9582747b3d4782f4b02ddecaab636bdbb1b6f530
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52344
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 21:51:31 +00:00
Raul E Rangel
d8956f7994 soc/amd/cezanne: Add support for C-state 3 
These values match the majolica UEFI firmware.

BUG=b:185787242, b:178728116, b:185921043

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If107c7e836942eeba734c1634fa7f8555c3018b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2021-04-21 18:42:55 +00:00
Marc Jones
d77b97dc9a soc/intel/xeon_sp: Set PAM0123 lock 
Set the PAM0123 lock as indicated by the Intel documentation.
This is set is finalize to allow any part of coreboot to update
the PAM prior to booting.

Change-Id: I3cdb7fc08eb903d799d585c56107de92f034b186
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-04-21 18:01:16 +00:00
Wayne3 Wang
a5761efd14 mb/google/volteer/variants/drobit: Update DPTF parameters 
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting.

BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.

Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-04-21 17:08:30 +00:00
Angel Pons
a590852313 soc/intel/broadwell/pch/acpi: Fix LPD0 and LPD3 methods 
When using references to a FieldUnit, DeRefOf is not used when storing a
value into the referenced FieldUnit, only when reading its value.

Tested on out-of-tree Compal LA-A992P, Linux 5.11.15-arch1-2 no longer
spews errors like these in dmesg:

 ACPI Error: Needed type [Reference], found [Integer] 000000006cbcc5d8 (20201113/exresop-66)
 ACPI Error: AE_AML_OPERAND_TYPE, While resolving operands for [And] (20201113/dswexec-431)
 ACPI Error: Aborting method \_SB.PCI0.LPD0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)
 ACPI Error: Aborting method \_SB.PCI0.I2C0._PS0 due to previous error (AE_AML_OPERAND_TYPE) (20201113/psparse-529)

Change-Id: I60c40452f8b5bdbec76264b578957396de8676ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2021-04-21 14:22:19 +00:00
Angel Pons
5d13e7fdcd soc/intel/alderlake: Drop unused PrmrrSize from devicetree 
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.

Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-04-21 14:21:56 +00:00
Angel Pons
0c0d49229d soc/intel: Replace open-coded buffer length calculation 
Use `sizeof(value)` instead of manually calculating the buffer size.

Change-Id: Ibe49e40b1c4f2c0b661d94e59059a95bdb204197
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-04-21 14:21:44 +00:00
Angel Pons
73a22edcc8 soc/intel: Fix typo in comment 
rotine ---> routine

Change-Id: I21a71f52d2ec7a05ea3dadf30e8f3e8dac07d168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-04-21 14:21:26 +00:00
Kyösti Mälkki
84d10cc5d3 ChromeOS: Use CHROMEOS_NVS guard 
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where
the conditional and dependency are clearly about the presence of
an ACPI NVS table specified by vendorcode. For couple locations also
CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS).

This also helps find some of the CONFIG(CHROMEOS) cases that might
be more FMAP and VPD related and not about ChromeOS per-se, as
suggested by followup works.

Change-Id: Ife888ae43093949bb2d3e397565033037396f434
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:27:31 +00:00
Rizwan Qureshi
307be997d1 soc/intel/alderlake: Enable PCIE RTD3 driver 
Include the PCIE RTD3 driveri for Alder Lake SoC.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I4732e4663feff503b249b76aaf70ec142a888963
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:20:07 +00:00
Rizwan Qureshi
a979460614 soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC 
CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:19:58 +00:00
Hao Chou
a50f190fd4 mb/google/volteer/variants/copano: Modify touch controller power sequence 
Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U.

BUG=b:184126265
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.

Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
 2021-04-21 09:19:38 +00:00
Jakub Czapiga
a37c8021a6 tests: Add lib/rtc-test test case 
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I2062e0d9dc2018bd6d8a210c8d26f2091e8c03fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
 2021-04-21 09:18:56 +00:00
Michael Niewöhner
3c20cba289 soc/intel/common/smbus: lock TCO base address on PCH finalize 
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2021-04-21 09:18:30 +00:00
Angel Pons
b48e6357e8 soc/intel/xeon_sp: Drop unused functions and prototypes 
No definition exists for pmc_set_disb() and rtc_failure() is not called.

Change-Id: I3a68e1fc55c62193735a46caf9f70dd9ee0b7349
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2021-04-21 09:18:09 +00:00
Angel Pons
6a2ece7bd1 soc/intel/xeon_sp: Align pmc.c and pmutil.c with Skylake 
Move code that gets used in stages other than ramstage to pmutil.c and
only build pmc.c in ramstage. This is done for consistency with other
platforms.

Change-Id: Iefb4fc86f3995ee6f259b7b287e04f7f94d8d025
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
 2021-04-21 09:18:00 +00:00
Angel Pons
505e383ccb soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c 
Commit 2c26108208 moved this function to
pmutil.c for Tiger Lake. Do this to all other platforms for consistency.
For Skylake, __SIMPLE_DEVICE__ preprocessor guards are no longer needed.

With this change, pmc.c is only needed in ramstage. Adjust Makefile.inc
accordingly, and drop ENV_RAMSTAGE guards from Skylake.

Change-Id: I424eb359c898f155659d085b888410b6bb58b9ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-04-21 09:17:40 +00:00
Angel Pons
f643b63c4d soc/intel/skylake: Move pmc_set_disb() to pmutil.c 
To drop bad __SIMPLE_DEVICE__ usage and for consistency with newer
platforms, move pmc_set_disb() to pmutil.c and adapt it accordingly.

Change-Id: I1a137b5b3120c350a04273567b9cb18c9a42a543
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
 2021-04-21 09:17:17 +00:00
Angel Pons
e4844ce7c9 soc/intel/skylake: Move acpi_sci_irq() to acpi.c 
Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2021-04-21 09:17:01 +00:00
Hao Chou
0feb949565 mb/google/volteer/variants/copano: Fix pen ejection event 
Modify PENH device GPIO GPP_E17 for pen ejection event.

BUG=b:182867209
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot, check evtest if SW_PEN_INSERTED event
(value:1/0) when insert/eject pen, and eject pen to wake system from s0ix

Change-Id: I1b13d09ed6d065779de9441f2137dcf6559b8f27
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52494
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:16:23 +00:00
John Zhao
3062083d42 soc/intel/tigerlake: Fix devices list in the DMAR DRHD structure 
The VT-d specification states that device scope for remapping hardware
unit which has DRHD_INCLUDE_PCI_ALL flags must be the last in the list
of hardware unit definition structure. This change fixes the devices
list in the DMAR DRHD structure.

BUG=b:185631878
TEST=Built image and booted to kernel on Voxel board.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I408fac7ff1185f4aa87bc4ffac7f25e31a4802b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2021-04-21 09:16:08 +00:00
Nicole Faerber
c68ca81589 mb/purism/librem_14: Switch from S76 EC to Librem EC 
Change-Id: Ib2625754e7df818e8a6311e649bc357b2093acb4
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-04-21 09:15:33 +00:00
Nicole Faerber
e00ea2fb38 ec/purism/librem-ec: Apply initial Purism customizations 
- remove unused Kconfig options
- change ACPI device name and HID
- remove ACPI for unused color keyboard backlight
- add support for RGB notification LED
- rename Wifi LED ACPI variable
- set some battery info defaults not populated by the EC

Change-Id: I72eca9deb83e5a6d919d6fcbd3b354fbf6e7a925
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-04-21 09:15:26 +00:00
Matt DeVillier
7d57d561b1 ec/purism/librem-ec: Add support for Purism Librem EC 
Initial commit is a clone of ec/system76/ec with string changes;
Purism-specific functionality will be added in subsequent commits.

Change-Id: I8c51724e6dbfe1bc09496537f9e031643f95c755
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2021-04-21 09:13:34 +00:00
Seunghwan Kim
5f20e85ff3 mb/google/dedede/var/sasuke: Update DPTF parameters 
Add control charging current from TSR0 and correct charger_perf table value.

BUG=b:179067801
BRANCH=dedede
TEST=emerge-dedede coreboot

Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Edward Doan <edoan@google.com>
 2021-04-21 09:13:11 +00:00
Matt DeVillier
d1b3f241b1 mb/google/*: allow LAN MAC to be read from VPD w/o ChromeOS 
Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather
than CONFIG_CHROMEOS.

Test: build/boot google/{beltino,jecht} with RO_VPD propagated from
stock firmware, verify MAC address set correctly.

Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:12:31 +00:00
David Wu
82c9b703ea mb/google/dedede/metaknight: Add device list and probe daughter-board 
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and
DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to
probe daughter-board to avoid USB device cannot recognize correctly.

BUG=b:184809456
TEST=build and verify USB device can recognize correctly

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2021-04-21 09:11:16 +00:00
Sridhar Siricilla
72e736d8e8 mb/intel/shadowmountain: Disable GSPI1 interface connected to FPS 
The patch disables GSPI1 interface connected to fingerprint scanner since
no plans to enable FPS on Shadowmountain.

TEST=Verified on Shadowmountain

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
 2021-04-21 09:11:07 +00:00
Angel Pons
5a19f7e3ce superio/nuvoton/npcd378: Fix psu_fan_lvl option 
If the option is successfully read from CMOS, the code overwrites its
value with 3. Fix this issue and use the new get_int_option() function.

Change-Id: I287a348da6ece78376d9c38e96128041752b032e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:07:40 +00:00
Angel Pons
612249dc8b mb/asus/am1i-a: Use read_int_option() 
Drop "error" (BIOS_DEBUG) messages as well.

Change-Id: I61954f8f893c144bbeba1530a486b389bd855ec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:07:07 +00:00
Angel Pons
f8a5eb2e4a mainboard: Use read_int_option() 
Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-04-21 09:06:30 +00:00
Angel Pons
0b7813fe97 superio: Use get_int_option() 
Change-Id: Ia46b622c52f98d4cc5fb7d9b02e2aeb366ef3915
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2021-04-21 09:04:35 +00:00
Angel Pons
3a782b1710 mainboard: Use get_int_option() for HWM settings 
Change-Id: I97fbbf2af76a6d4c44221000da7b36378e066ff3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:03:24 +00:00
Angel Pons
38f89f37bf mb/**/early_init.c: Use get_int_option() 
Change-Id: I460cad0cc671be830d0fa0f68a531acaea7effcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:03:02 +00:00
Angel Pons
5ddfaf0807 ec/kontron: Use get_int_option() 
Change-Id: Ibca7660ed03525903a1146a1fb2937550406bee8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:02:31 +00:00
Angel Pons
f9c939029b nb/intel: Use get_int_option() 
Change-Id: I8896531d6df729709456bc6e79e02136d9ea7b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2021-04-21 09:01:28 +00:00