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43788 Commits

Author SHA1 Message Date
Felix Held
badea79500 mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tables 
This file isn't correct, since the Stoneyridge SoC doesn't have a legacy
PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select
HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this
board.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-09-14 20:41:10 +00:00
Felix Held
e74da16741 mb/google/kahlee: drop unused and incorrect irq_tables.c 
This file is neither included in the build nor correct, since the
Stoneyridge SoC doesn't have a legacy PCI bridge on bus 0 bridge 0x14
function 4.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0daed891984faed9fbc36f0215edfc56e0ae14a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-09-14 20:40:44 +00:00
Matt DeVillier
3ee2420514 mb/google/skyrim/winterhold: Use 'detect' vs 'probed' for touchpads 
As of commit 2cf52d80a6 ("mb/*/{device,override}tree: Set touchpads to
use detect (vs probed) flag") all touchpads in the tree have been
switched from using the 'probed' flag to 'detect.' Winterhold was added
in between the time that patch was pushed and merged, so switch these
instances over too.

Change-Id: I34e1265ecd6409f720ae486926c5078f626fc693
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67487
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 20:32:52 +00:00
Arthur Heymans
43ed5d2534 cpu/amd: Move locking SMM as part of SMM init 
Locking SMM as part of the AP init avoids the need for
CONFIG_PARALLEL_MP_AP_WORK to lock it down.

Change-Id: Ibcdfc0f9ae211644cf0911790b0b0c5d1b0b7dc9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 20:29:59 +00:00
Arthur Heymans
e48dcb708c cpu/amd/smm: Move MP & SMM init in a common place 
Change-Id: I7c457ab69581f8c29f2d79c054ca3bc7e58a896e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64870
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 20:29:17 +00:00
Arthur Heymans
44807acaef soc/amd/common: Add common function to get cpu count 
This is the same for all supported AMD hardware.

Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-14 20:28:37 +00:00
Zheng Bao
62cd5e8603 soc/amd: Recalculate the field power in PSS table entry 
Being divided by 1000 causes data loss and the loss is expand by
muliplication.

So we just set a lower divisor before muliplication.

BUG=b:185922528

Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-14 20:24:00 +00:00
Patrick Georgi
41a8043bdf 3rdparty/opensbi: Update to latest ToT 
That's 3 years of development, including adapting to new, shiny,
Cascade of Attention-Deficit Teenagers[0] induced incompatible
assembler syntaxes.

Signed-off-by: Patrick Georgi <patrick@coreboot.org>

[0] https://web.archive.org/web/20220824045741/https://www.jwz.org/doc/cadt.html

Change-Id: I8606700149ca74e93b85d78546a29df2916d39b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
 2022-09-14 20:12:56 +00:00
Felix Held
40a38cc8f0 soc/amd/mendocino: Add support for separate RW A/B partition SPL file 
Add support for having different Security Patch Level (SPL) table files
in the read-only and the read-write A/B partitions. This allows the SPL
table file in the main or RO FMAP partition to only cover the embedded
firmware binaries in that partition and have a separate SPL file in the
RW A and B partitions that covers the embedded firmware binaries in the
RW partitions.

BUG=b:243470283

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-09-14 18:04:49 +00:00
Tony Huang
c3e36ea20b mb/google/dedede/variants/shotzo: Turn off LAN power in S0ix 
Turn off the LAN power which is controlled by GPP_A10 in S0ix states.
For an USB device, the S0ix hook is needed for the on/off operationas
to take place.

BUG=b:245426120
BRANCH=firmware-dedede-13606.B
TEST=emerge-shotzo coreboot
     check LAN LED off in S0ix states
     check LAN function ok after suspending 500 loops
     check SSDT table has MS0X entry
     Scope (\_SB)
    {
        Method (MS0X, 1, Serialized)
        {
            If ((Arg0 == One))
            {
                \_SB.PCI0.CTXS (0x41)
            }
            Else
            {
                \_SB.PCI0.STXS (0x41)
            }
        }
    }

Change-Id: I3fcab4a73239b4f006839c0c81e9b4cc74047b77
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2022-09-14 17:48:32 +00:00
Angel Pons
c3aa659286 soc/intel/cannonlake: Read HPR_CAUSE0 register 
Log the Host Partition Reset Causes (HPR_CAUSE0) register, as done on
newer platforms.

Change-Id: I35261cefae67649fb7824e5ef3d7eb10add36a53
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-09-14 14:07:43 +00:00
Elyes Haouas
23f272994f console/vtxprintf.c: Use | operator for bit operation instead of + 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I478265dcd070dcf3fb2cf2c535b6ca1d86b9a3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-14 14:06:34 +00:00
Elyes Haouas
0f1fb8a868 soc/mediatek: Use "if (!ptr)" in preference to "if (ptr == NULL)" 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I9cf4097518034fa4c3ae1899840ae3a276936f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67581
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 12:49:44 +00:00
Elyes Haouas
5e6b0f0cac nb/intel: Use "if (!ptr)" in preference to "if (ptr == NULL)" 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6d0d945011fa046b974c6f4554cb9fb15e523afb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67578
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 12:01:24 +00:00
Garmin Chang
1fac2e20b8 soc/mediatek/mt8188: Set PLLs to hardware default values 
Some PLLs are not used in firmware, so we should keep them as hardware
default values. If their modules want to set them, the corresponding
drivers should set them in the kernel stage.

BUG=b:233720142
TEST=build pass.

Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 12:00:50 +00:00
Garmin.Chang
f189249eb6 soc/mediatek/mt8188: Fix indention in pll.c 
BUG=b:233720142
TEST=build pass.

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I567d1ded1c3b5e36a25026cec697d43d92d5524c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67546
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 12:00:24 +00:00
Garmin Chang
c7b549ec99 soc/mediatek/mt8188: Change vpp_sel default mux for 4k support 
vpp_sel and ethdr_sel are vdosys clock source select mux.

Steps to change to support 4K source:
1. Change vpp_sel source to mainpll_d6 to run at 416MHz.
2. Change ethdr_sel source to univpll_d6 to run at 416MHz.

BUG=b:233720142
TEST=build pass.

Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I24f133b9b383fd019983cb29a213b47717148e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 12:00:06 +00:00
Rex-BC Chen
5f9395cbc1 mb/google/geralt: Raise little core CPU frequency from 500MHz to 2GHz 
To improve boot time, raise little CPU from 500MHz to 2GHz at romstage
(before DRAM calibration).

FW logs:
Check CPU freq: 1999968 KHz, cci: 1600012 KHz

TEST=cpu freq and cci freq run correctly.
BUG=b:244251006

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic1bed53669baa15f797c9a952455376a39d29cf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67544
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 11:56:27 +00:00
Garmin Chang
d9b1dfe968 soc/mediatek/mt8188: Fix some wrong settings for PLLs 
The observed CPU big core frequency is double compared with the current
PLL setting. Therefore fix the wrong setting for PLL register
APMIXED_ARMPLL_BL.

Moreover, we also fix some wrong settings for other PLLs.

TEST=CPU frequency of big core CPU is correct and bootup correctly.
BUG=b:244215537

Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 11:56:03 +00:00
Rob Barnes
d522f38c7b timer: Change timer util functions to 64-bit 
Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.

Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.

BUG=b:237082996
BRANCH=All
TEST=Boot dewatt

Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
 2022-09-14 11:55:39 +00:00
Eran Mitrani
51249d6bed mb/google/rex: Add audio parts ALC5682I-VS and MAX98357 
BUG=b:232573696
TEST=Able to verify audio playback on Google/Rex with this change.

Change-Id: Ia8dfc79e7e4d27828726145156c870733d716899
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66919
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-14 05:30:08 +00:00
Kapil Porwal
715c17a750 soc/intel/mtl: Fix GPIO group pad base for ACPI 
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15
kernel pintrl driver:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c

In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation.  The GPIO groups that
are usable by the  OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.

BUG=b:232573696
TEST=Tested on Google Rex board. After this change, driver rt5682s
is able to claim pinctrl IRQ 358 corresponding to GPP_B06.

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-09-14 05:29:42 +00:00
Ivy Jian
64c77dc299 soc/intel/meteorlake/retimer: Change loglevel prefix 
This message is not really an error message, so BIOS_ERR is 
inappropriate. Since the message is informational, switch to 
BIOS_INFO instead.

BUG=b:244687646
TEST=emerge-rex coreboot
before
[ERROR]  USB Type-C 0 mapped to EC port 0
after
[INFO]  USB Type-C 0 mapped to EC port 0

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
 2022-09-14 05:29:30 +00:00
Ivy Jian
4257e8c132 soc/intel/meteorlake: Enable TcssDma1En 
Adding support enables/disables TcssDma1En by usb4_params.

BUG=b:244687646
TEST= TcssDma1En is enabled as expected.
before patch
[SPEW ]  PCI: 00:0d.2 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.2 [8086/7ec2] enabled
[INFO ]  PCI: Static device PCI: 00:0d.3 not found, disabling it.
after patch
[SPEW ]  PCI: 00:0d.2 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.2 [8086/7ec2] enabled
[SPEW ]  PCI: 00:0d.3 [8086/0000] bus ops
[DEBUG]  PCI: 00:0d.3 [8086/7ec3] enabled

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I9cd8fc3819f533e9581fea19d4da48283888cc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67534
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-09-14 05:29:23 +00:00
Ivy Jian
78c4d0f6a6 soc/intel/meteorlake: Enable tbtPcie2/3 
Adding support enables/disables tbtPcie2/3 by usb4_params.

BUG=b:244687646
TEST= TRP2/3 are enabled as expected.
before patch
[INFO ]  PCI: Static device PCI: 00:07.2 not found, disabling it.
[INFO ]  PCI: Static device PCI: 00:07.3 not found, disabling it.
after patch
[DEBUG]  PCI: 00:07.2 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.2 [8086/7ec6] enabled
[DEBUG]  PCI: 00:07.3 subordinate bus PCI Express
[DEBUG]  PCI: 00:07.3 [8086/7ec7] enabled

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia1bdc9b5c0533bdddae67b8039103162a57fdc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67530
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
 2022-09-14 05:29:16 +00:00
Tony Huang
e5c547c2d7 mb/google/dedede: Generate MS0X entry and provide variant hook 
BUG=b:245426120
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot
     check SSDT table has MS0X entry
     Scope (\_SB)
    {
        Method (MS0X, 1, Serialized)
        {
            If ((Arg0 == One)) {}
            Else
            {
            }
        }
    }

Change-Id: Id01089531503e62231c5ab19e4cd8056198b9acb
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
 2022-09-13 16:36:04 +00:00
Matt DeVillier
20e1dc27e9 mb/google/poppy/nami: Add 'detect' flag for Elan touchpad 
Add the 'detect' flag to the Elan touchpad, so coreboot can determine
which touchpad type is present at runtime and generate the correct
ACPI entry for it (the Synaptics touchpad already has the flag).

Test: build/boot google/nami, verify touchpad works under Linux/Windows

Change-Id: I437d1d470552d55496dfe611f441331127c64250
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2022-09-13 16:08:43 +00:00
Sean Rhodes
8fb4c9d956 mb/starlabs/starbook/tgl: Tidy up the layout 
Tidy up the layout to remove unnecessary sizes. This change also makes
the flash start at 0x0 and increases the size of the FMAP to 0x1000.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I46663003857eb50271c6ad1da6c4e56c8f4bb6c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-09-13 15:21:42 +00:00
Lean Sheng Tan
9b9a763ca9 mb/prodrive/atlas: Enable legacy S3 support 
Enable S3 support as Prodrive doesn't need s0ix for now.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7625c8ac860e1afc60c94b3c51e996531a1f2b15
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
 2022-09-13 14:21:25 +00:00
Victor Ding
787b46673b mb/intel/adlrvp: Correct HWIDs for ChromeOS devices 
The current HWIDs for ADL RVP are reported as invalid by Chrome on
ChromeOS; fix it by generating new valid HWIDs with the following
commands:

```
./util/chromeos/gen_test_hwid.sh ADLRVPM
./util/chromeos/gen_test_hwid.sh ADLRVPN
./util/chromeos/gen_test_hwid.sh ADLRVPP
```

BUG=b:243899466

Change-Id: Iad6f47e67c2d35363b042aabec8b3317d5bfc111
Signed-off-by: Victor Ding <victording@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67532
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-13 13:09:02 +00:00
Elyes Haouas
d0033e363f src/console: Reformat code 
Most of these changes are suggested by clang-format(13.0-54) tool on
Debian testing.

Change-Id: I68a288b3f7e911331e7324bf13cf9bde259a29de
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-09-13 13:06:33 +00:00
Elyes Haouas
c705ecd2eb device/dram: Reformat code 
Most of these changes are suggested by clang-format(13.0-54) tool on
Debian testing.

Change-Id: I9bf5f516db4f12ffe1e9a714c7a8ae179c12b149
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2022-09-13 13:06:05 +00:00
Venkat Thogaru
fec9abc697 sc7180: Fix DDR training failure during warm reset with OTA 
Problem: OTA is triggering warmboot, where DDR is
in self-refresh mode. Due to which DDR training
is not going well.

Change: Verify reboot type in case of OTA. If it is warmboot, will
force for cold boot inorder to trigger DDR training

BUG=b:236990316
TEST=Validated on qualcomm sc7180 development board.

Test observation: Cold boot is triggered forcefully,
if current reboot is warmboot in case of OTA

Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I908370662292d9f768d1ac89452775178e07fc78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67406
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2022-09-13 13:05:46 +00:00
Fred Reitberger
bec412156a mb/google/skyrim: Enable ASPM 
Enable Kconfig options for ASPM.

TEST=Verify ASPM is enabled with `lspci -vvv`, `suspend_stress_test -c
10` passed all 10 times
BUG=b:243771794

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I54071d9c9607da4561d745d152924d56904c0fee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-09-12 18:41:28 +00:00
Fred Reitberger
ef79e77c58 mb/google/skyrim/port_descriptors.c: Update ASPM configuration 
Update ASPM configuration, disabling ASPM for the SSD due to s0i3
issues.  Bug b:245550573 created to track the SSD issue.

TEST=Boot to OS and verify suspend via `suspend_stress_test -c 10`
BUG=b:243771794

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I45a290c8ceddd39f65c6fe1390e3a753cad99899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
 2022-09-12 18:40:46 +00:00
Elyes Haouas
b366bcbd29 mb/amd/*/irq_tables.c: Reformat code 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If6cdf02c56778da67b56afbb71f9f01107f23d2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:32:36 +00:00
Elyes Haouas
b40e185b9c mb/google/kahlee/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4ccdd370d3e9aef938fae4c4690ec0bf4c53c500
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:31:14 +00:00
Elyes Haouas
7322384ca5 mb/lenovo/g505s/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia4212e4a911a13a3288985bb3577cda771b600a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:31:01 +00:00
Elyes Haouas
b3bb646b7b mb/msi/ms7721/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia34f758a6208d20a47b8fb28420ebd4c585d3699
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:30:43 +00:00
Elyes Haouas
1335f4bb81 mb/jetway/nf81-t56n-lf/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I86d664c7ebdd8ff8b47b498da7c861c11a80892c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:30:19 +00:00
Elyes Haouas
caefe5c366 mb/lippert/frontrunner-af/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I2c1499a95c0d1d60a58506a043691e32ca8973de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:29:54 +00:00
Elyes Haouas
dceb2ff95e mb/elmex/pcm205400/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ibd155f6ec39cd6b4e5faee2eb63264eb90e70294
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:29:36 +00:00
Elyes Haouas
9a657e2b9d mb/biostar/a68n_5200/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1ac0cc79f8cb13ea11fb32236ed5c9f0a4ab8586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:29:20 +00:00
Elyes Haouas
53529b2698 mb/bap/ode_e20XX/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If069604de6e24e0d591e84d54ae4d39bd14e21fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:28:57 +00:00
Elyes Haouas
f3f56a2567 mb/hp/*/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I3ba6a8dfb966038d63cfdeceb1e37eeb1a37343b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:28:41 +00:00
Elyes Haouas
135ab119a2 mb/gizmosphere/*/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I19412b595b3a1d2026fce5a84ddbd6356abe5a3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:28:17 +00:00
Elyes Haouas
726bf18065 mb/pcengines/apu{1,2}/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I5331c7127905524517efa50158bde8d6a1c5f1eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:27:51 +00:00
Elyes Haouas
2cd41c6371 mb/asus/f2a85-m/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I223282147b3265133b8b249368cfe4cdf4cafa5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:27:30 +00:00
Elyes Haouas
d0827aace3 mb/asrock/*/irq_tables.c: Use ALIGN_UP macro 
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I38ea4e9bf0d8e2d93b86413cd9b1a2fb0a547e1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:27:05 +00:00
Elyes Haouas
e378cdbb61 mb/amd/*/irq_tables.cmb/*/*/irq_tables.c: Use ALIGN_UP macro 
Change-Id: I2bd5e09f51918fe4c7e954edf54ab4d9bc629fd1
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2022-09-12 15:26:42 +00:00