We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.
BUG=b:223936777
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.
Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
C0 has no redriver, so enable SBU muxing in the SoC.
C1 has a redriver which does SBU muxing, so disable SBU muxing in the
SoC. However, this also disables AUX biasing when the pins are
configured as NF6. So instead configure the C1 AUX bias pins as GPO.
BUG=b:227259673
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
Doesn't work:
- TPM interrupt on Linux [1]
- All EC related functions - EC driver is WIP
- WLAN/BT (PCIe) - gets detected but can't be enabled
- 3G/LTE (not powered without EC driver)
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When rebuilding coreboot the empty fit table added to added to CBFS
stays the same so the build process sees no reason to update the file.
In the meantime ifittool did update that file for instance to add
microcode update entries. So each time coreboot is rebuilt the entries
are appended to the FIT table which runs out of space at some point.
One way to deal with this is to clear the fit table when setting the
pointer inside the bootblock.
TESTED: Now running 'make' again on prodrive/hermes does not report an
error with a filled FIT table.
Change-Id: Ia20a489dc90a4ae704e9ee6d532766899f83ffcc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63036
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.
Generating flame graph using https://github.com/brendangregg/FlameGraph:
cbmem -S > trace.txt
FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg
TEST=Run on coreboot-enabled device and extract timestamps using
-t/-T/-S options
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
TEST=Verify the write protection details on Gimble.
Excerpt from Gimble coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Now that the amdfwtool support for Sabrina is in place, change the
SoC name parameter passed to amdfwtool from Cezanne to Sabrina.
The fw.cfg file still points to the Cezanne binaries, but since
commit 9cb0a05dfb (soc/amd/sabrina: Add
prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig
config file in the build. As soon as the Sabrina PSP binaries are
available in 3rparty/amd_blobs, the fw.cfg file will be updated to use
the correct ones for Sabrina.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the specific SPD hex file for the Samsung memory part with
updating the part number into the SPD table. The ABL needs to
identify the part by checking SPD data to do the proper tuning.
BUG=b:224884904
TEST=Build, validate the SPD data has been applied.
Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Some solutions require readable form of timestamps, which does not
contain spaces. Current descriptive timestamp names do not meet this
criteria. Also, mapping enums to their text representation allows for
quick grepping (use of grep command) to find relevant timestamps in the
code.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
On FreeBSD, every build target would show warnings from its
builtin printf().
Change the regexp to be compatible with BSD sed.
This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not
completely converted".
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.
BUG=b:223289882
TEST=boot guybrush and verify the devbeep and gpio value in kernel
Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
