Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.
Change-Id: Ie85b8ee5dad1794864c18683427e32f055745221
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13132
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There can be an error when a cbfs file is added aligned or as
xip-stage and hashing of this file is enabled. This commit
resolves this error. Though adding a file to a fixed position
while hashing is used can still lead to errors.
Change-Id: Icd98d970891410538909db2830666bf159553133
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13136
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BRANCH=none
BUG=chrome-os-partner:47609
TEST=remove servo board connection and insert/remove an empty SD card
in recovery mode.
Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6
Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313073
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Mimicking change I7037308d2, always compile mdelay for romstage.
The boards that #included delay.c in the romstage now rely on the linker
instead, which is a desirable cleanup.
Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Since backlight is controlled in depthcharge, we only configure
control pins as output pin and set them power-off in the coreboot
stage.
BRANCH=none
BUG=none
TEST=Saw DEV screen during boot process.
Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754
Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292686
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13093
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
The function is called by mainboard's configure_audio().
BRANCH=chromeos-2015.07
BUG=chrome-os-partner:41507
TEST=build and verified pass on oak board
Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297225
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13090
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The mt8173 boot rom expects the bootblock to be in a certain format.
gen-bl-img wraps our bootblock appropriately.
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3
Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292664
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The script checks for a folder called documentation, while the folder
name is Documentation.
Without this change, I get this when running the script:
util/scripts/get_maintainer.pl: The current directory does not appear to be
a coreboot source tree.
Change-Id: Ied7ead7dfec33e9324f06d0ef60dcd6d7ba40104
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/13062
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We just had a user who spent a fair amount of time debugging a
failing build due to this option being enabled. Add a little
guidance that it probably shouldn't be enabled in the help text.
Change-Id: I9339e442876c1fcd18ea564041c6cc1201c18ae5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a new Kconfig variable to enable the generation of
position and alignment attributes for cbfs files which
has constraints on this parameters.
In addition, modify Makefile.inc to support that option.
Change-Id: Ibd725fe69a4de35964bdb2dde106d9a7c37ffb47
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds support for booting the Purism Librem 13 mainboard
with coreboot, using binaries extracted from the original BIOS
and from a Broadwell Chromebook.
The following features have been tested on Ubuntu 15.10:
- Input: Keyboard and Trackpad
- SATA: Internal HDD and M.2 NGFF
- Network: WiFi and Ethernet
- USB: Bluetooth, Camera, SD Card, Ports (1xUSB2 and 1xUSB3)
- Video: Internal panel and HDMI port
- Internal speakers and microphone (headphones do not work)
- EC handling for battery, AC, lid, special keys
These binaries are extracted from the original BIOS:
- VGA BIOS
- Management Engine
- Intel Firmware Descriptor
These binaries are extracted from a Broadwell Chromebook BIOS:
- MemoryInit reference code binary
- SiliconInit reference code binary
This was developed and tested on an Librem 13 device. For those
who may want to do more development you can use EHCI debug and the
right USB port to get coreboot output.
Change-Id: Ia72e2d7ddc8ba5eef63819e5677122a5a5c705d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13026
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
WRDD method in wifi.asl returns the regulatory domain code. This value
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.
Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We already do this for lines with all zeroes, so it makes sense to
treat all ones the same, for symmetry.
Change-Id: I4b637b07a49e0c649331aa200995b474dd9a2682
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating EC+PD takes long enough to update that it is good to
show the "critical update" screen when doing an EC/PD update.
BUG=chrome-os-partner:49650
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.
Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e
Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In order to support vboot requesting graphics support in normal
mode the VBT needs to be passed to FSP when it is requested
outside of the usual developer/recovery path.
To make this integrate cleaner use the generic bootmode provided
display_init_required() function instead. Also have it print a
message indicating when it does not pass VBT to GOP so it is
easier to see what happened in the console logs.
BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Enable EC_SLOW_UPDATE on chell and test that when vboot
requests graphics support in normal mode FSP will get passed VBT
and bring up the panel.
Change-Id: I07bc54d37d687134b21baa60b5c278b5041241cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41efd322951b8f3a8a687944832bfd89fd3014ca
Original-Change-Id: I1b68760eabbf3af1d962cb2a3199e504a7852042
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add flag handling for CONFIG_VBOOT_EC_SLOW_UPDATE to indicate
to vboot that it should show the "critical update" screen during
software sync for EC+PD.
In order to make this work on x86 where we do not run graphics
init in the normal path add handling for CONFIG_VBOOT_OPROM_MATTERS
and indicate to vboot when the option rom has been loaded.
BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.
Change-Id: I5ca46457798a22e9b08aa2febfec05b01aa788f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a1bb8572c3485f64b9f3e759288321b44184e66
Original-Change-Id: I9f66caaac57bb9f05bc6c405814469ef7ddf4d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13073
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Override the default PL2 values with one recommended by
Intel. Disable PL1 configuration via MMIO register.
BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
Change-Id: I10742f91cc7179de1482d42392338976e8082afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf
Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321392
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is a follow-up to CL:320623 to make veyron DRAM configs
uniform (except for Rialto).
As discussed in chrome-os-partner:43626, the mr[3] value and ODT
are set diffently for Mickey, thus the .inc files for other boards
have mr[3] = 1 and ODT disabled.
BUG=none
BRANCH=veyron
TEST=compile tested for veyron
Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
Original-Reviewed-on: https://chromium-review.googlesource.com/321870
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13109
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add functionality to cbfstool to generate file attributes
for position and alignment constraints. This new feature
can be activated with the -g option and will generate,
once the option has been enabled, additional attributes
for the files where position, xip or alignment was specified.
Change-Id: I3db9bd2c20d26b168bc7f320362ed41be349ae3a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
