Kyösti Mälkki
f5c0d61296
intel/smm: Provide common smm_relocation_params
...
Pull in all copies of smm_relocation_params structs defined
for intel platforms.
Pull in all the inlined MSR accessors to the header file.
Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-11-22 06:37:50 +00:00
Elyes HAOUAS
34715df801
src: Remove unused '#include <cpu/cpu.h>'
...
Change-Id: Ibcb1cafe36c255b4c5bd0a4faeedb95e91048709
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2019-10-28 11:56:38 +00:00
Kyösti Mälkki
faf20d30a6
soc/intel: Rename some SMM support functions
...
Rename southbridge_smm_X to smm_southbridge_X.
Rename most southcluster_smm_X to smm_southbridge_X.
Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-15 06:55:59 +00:00
Kyösti Mälkki
621142aa60
intel/ice,sky,cannon: Drop unused EMRR and UNCORE_EMRR code
...
There was no code present to call wrmsr with the data we
prepared in the structs. The MSRS are already set up by FSP,
just reference with the more recent names of PRMRR and UNCORE_PRMRR.
Change-Id: Ib49e7af52e1170a1304975ff0ae63f99e106dffe
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2019-08-15 05:57:43 +00:00
Kyösti Mälkki
e31ec299de
cpu/x86: Separate save_state struct headers
...
Any platform should need just one of these.
Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-13 13:59:05 +00:00
Kyösti Mälkki
2e3aff8d86
cpu/x86/smm: Drop SMI handler address from struct
...
Change-Id: Ib925b11ba269e0f3a9a0a7550705bf2a6794c5b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2019-08-09 13:13:41 +00:00
Kyösti Mälkki
41d9b65149
soc/intel: Fix SMRAM base MSR
...
Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.
Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34730
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-08-08 04:57:03 +00:00
Kyösti Mälkki
14222d8678
arch/x86: Change smm_subregion() prototype
...
Do this to avoid some amount of explicit typecasting
that would be required otherwise.
Change-Id: I5bc2c3c1dd579f7c6c3d3354c0691e4ba3c778e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-08 04:53:18 +00:00
Kyösti Mälkki
d78866399c
intel/icelake,skylake,cannonlake: Drop unused parameter
...
Change-Id: I0900c3b893d72063cc8df5d8ac370cf9d54df17a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2019-08-07 05:41:06 +00:00
Kyösti Mälkki
71756c21af
soc/intel: Expand SA_DEV_ROOT for ramstage
...
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2019-07-21 18:58:01 +00:00
Kyösti Mälkki
28dc7dce83
soc/intel: Use config_of_path(SA_DEVFN_ROOT)
...
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I53324603c9ece1334c6e09d51338084166f7a585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2019-07-18 15:23:13 +00:00
Kyösti Mälkki
f1b58b7835
device/pci: Fix PCI accessor headers
...
PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.
Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2019-03-01 20:32:15 +00:00
Arthur Heymans
e750b38e48
cpu/x86/mtrr.h: Rename MSR SMRR_PHYS_x to IA32_SMRR_PHYSx
...
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures
Software Developer’s Manual.
The purpose is to differentiate with MSR_SMRR_PHYSx.
Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/27584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2018-07-24 18:34:37 +00:00
Elyes HAOUAS
c8a649c08f
src: Use of device_t is deprecated
...
Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Georgi <pgeorgi@google.com >
2018-06-14 09:29:31 +00:00
Elyes HAOUAS
3c8b5d00c3
soc/intel/cannonlake: Get rid of device_t
...
Use of device_t has been abandoned in ramstage.
Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/26584
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2018-06-01 16:26:25 +00:00
Lijian Zhao
f0eb99996d
soc/intel/cannonlake: Fill the SMI usage
...
Add SMM support for Cannonlake on top of common SMM, also include the
SMM relocate support.
Change-Id: I9aab141c528709b30804d327804c4031c59fcfff
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com >
Reviewed-on: https://review.coreboot.org/21543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2017-10-03 20:23:41 +00:00
