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Author SHA1 Message Date
Elyes HAOUAS
eb00e8722b sb/intel/i82801gx: Use 'const' to set pci_devfn_t statically 
Change-Id: I4b33b42f41c7e34c5eab70edf2f12862816220d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:43:57 +00:00
Elyes HAOUAS
25d20d3332 sb/{bd82x6x,ibexpeak,lynxpoint}/early_smbus: Use macro 
Change-Id: If57d785b92f0f09d9def90b8ac87833321e3cfcf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-09 14:42:56 +00:00
Edward O'Callaghan
200f02a518 mb/google/hatch: Allow variants to not necessarily be laptops 
In some cases Hatch variants are not laptop form-factors such
as Puff. Ensure that the base configuration does not assume
the form factor and allow variants to elect their intended
use-case.

Note that the issue is that early ec sync needs to be
disabled for EFS2 to function correctly, see commit 6daa8c3ba5
from the FIXME line. The relationship is that desktops do not
have a battery.

BUG=b:152951181
BRANCH=none
TEST=none

Change-Id: I15dc9efa51e9d61297868df287879dfb62909e33
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40252
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-09 13:43:33 +00:00
Felix Singer
ef6eceea56 sb/ibexpeak: Use .device for single PCI ID 
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I40c4447579cfbf2b9c52dcfaa34f34b22f75c89c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39332
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-09 10:52:52 +00:00
Arthur Heymans
dc98bed869 mb/intel/d510mo: Add vbt file 
Add vbt file extracted from the vendor UEFI blob version 0524.

Change-Id: Idd39065e9cf5a420317d79695cf032713173eeab
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-09 08:51:51 +00:00
Felix Held
00058f513e soc/amd/picasso: replace get_soc_config with config_of_soc 
get_soc_config was a reimplementation of config_of_soc, so drop
get_soc_config and cfg_util.c.

Change-Id: I007c83cfe5063130c18819925844b6c643cf0232
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-08 21:45:11 +00:00
Felix Held
72e987d540 soc/amd/stoneyridge: replace get_soc_config with config_of_soc 
get_soc_config was a reimplementation of config_of_soc.

Change-Id: I73c6a84703e22d6778b830f4bb82419361c85ff7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-04-08 17:15:23 +00:00
Seunghwan Kim
e0b41fd12e mb/google/nightfury: Update DPTF parameters 
Apply initial DPTF parameters for nightfury from internal thermal team. Will update after further thermal/performance tuning.

BUG=b:149226871
BRANCH=firmware-hatch-12672.B
TEST=built and verified FAN worked by DPTF active policy

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I712bdd8edc999ef7ee33f4adf21893be12e86bec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-04-07 23:18:26 +00:00
Maxim Polyakov
5b06ffea56 soc/xeon_sp: add configs to use common/gpio diver 
Allow the use of the common/gpio driver to create Lewisburg PCH pad
configurations for server motherboards with Skylake-SP processors.

This patch should only be applied after adding Lewisburg PCH definitions
to the soc/intel/xeon_sp code [1].

[1] https://review.coreboot.org/c/coreboot/+/39425

Change-Id: I4a8e83cad0729bbbb50ba5a2b336f6cf7c1eca13
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-07 18:19:13 +00:00
Maxim Polyakov
ce2399a446 soc/intel/common: gpio: print error if pad is not found 
Allow to print a debug error message when the GPIO community does not
contain the pad number from the motherboard configuration.

Change-Id: I21fb389a5d29e11b1fbc24e836d91e17957047f1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
 2020-04-07 18:18:59 +00:00
Maxim Polyakov
182d7bae47 soc/intel/xeon_sp: Add Lewisburg defs for common/gpio driver 
Adds definitions that allow to use the common GPIO driver to configure
the Lewisburg PCH pads. Using the GPIO configuration from common/gpio,
unlike the FSP-style definitions from Intel RefCode [1] definitions,
is more understandable and makes the motherboards code much cleaner.
In addition, we can use utilities, such as inteltool, to analyze the
configuration of proprietary firmware to add support for new server
motherboards with Skylake-SP processors.

The pin layout in this patch corresponds to the pinctrl driver in the
Linux kernel v4.14 for the Lewisburg PCH GPIO controller [2].

[1] https://designintools.intel.com/product_p/stlgrn45.htm
[2] drivers/pinctrl/intel/pinctrl-lewisburg.c

These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US.

Change-Id: Idde32fdd53f1966e3ba6b7f5598ae8f51488d5a5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39425
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-07 18:18:42 +00:00
Subrata Banik
b98c89626e drivers/intel/wifi: Add support for Intel Wi-Fi 6 Series 
Add all Intel WIFI 6 series PCI ids to device/pci_ids.h file.

TEST=Harrison Peak (HrP) Wi-Fi module is getting detected during PCI enumeration.

Change-Id: Id5452c5c02b58e84d8e5768653b18c9d1246c1bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40224
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-07 16:49:52 +00:00
Michał Żygowski
869ac71483 Revert "mb/pcengines/apu2: add reset logic for PCIe slots" 
This reverts commit c04871a398.

Reason for revert: Many apu2 users reported issues with PCIe modules
detection in mPCIe2 slot (4x GFX PCIe). The regression was not caught
by 3mdeb validation stands and hardware configuration.

Change-Id: I609bf4b27c88a9adf676d576169f5ca26726ee86
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40147
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-07 12:07:15 +00:00
Felix Singer
7daf3cd32e sb/intel/bd82x6x/sata: Set values as described in BIOS spec 
Set some things missed originally because of formatting issues
in the BIOS spec. Values were compared with a vendor dump.

Change-Id: I27360d6ea5d1f00b1ed350f47ff40a22f19dfb05
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40231
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-07 11:25:01 +00:00
Felix Singer
192666f352 sb/intel/bd82x6x: Drop PCI resource reg override 
Assignment of PCI resource registers is up to the allocator. Therefore,
drop override of the PCI resource register.

Change-Id: I184a263c81aa8a434fcd153406b73058914cb2f9
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2020-04-07 11:24:35 +00:00
Felix Singer
66579d4e36 sb/intel/bd82x6x/sata: Don't hard-code values 
The interrupt line registers are configured in a central place,
pch_pirq_init() in `lpc.c`, according to the PIRQ configuration.
Hardcoding values here makes no sense.

Change-Id: Ide5f101b2e5bda84f3c2ff8c8ca636b8233bb948
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-04-07 11:15:13 +00:00
Subrata Banik
ecaa2d4741 soc/intel/tigerlake/acpi: Fix typo in HDA in comment 
HSA -> HDA (High Definition Audio)

Change-Id: Ic0e6ad7b26105fdd6eca6cd11edcf2236e5c7123
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-04-07 11:07:45 +00:00
Michał Żygowski
7b28801223 drivers/pc80/tpm/tis.c: change the _HID and _CID for TPM2 device 
According TCG PC Client Platform Firmware Profile Specification Revision
1.04 Chapter 8.1 the TPM device object should have the _CID and _HID
values set to MSFT0101 for TPM2.

FreeBSD also detects TPM2 device using MSFT0101 _HID and _CID only.

TEST=boot FreeBSD 12.1 on PC Engines apu2 and check in dmesg that TPM2.0
is detected

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I45123f272038e664b834cabd9d8525baca0eb583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39699
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-07 09:50:22 +00:00
Michał Żygowski
2f399b7d5b nb/amd/pi/00730F01/northbridge.c: refactor IVRS generation 
Use defined structures to assemble IVRS and IVHD entries. Additionally
assemble IVHD type 11h which supersedes IVHD type 10h. In order to
utilize all IOMMU features firmware should also expose IVHD type 11h.
The new type is already supported and parsed since Xen 1.13. IVHD
type 10h should still be present for backwards compatibility.

TEST=boot PC Engines apu2 and disassemble IVRS using newest IASL,
boot Xen 1.13 or newer with debug enabled and see IVRS IVHD 11h parsed
in xl dmesg

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9a2c24b67adfa8ebd718caeb5eec88687dcbcc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-04-07 08:15:05 +00:00
Marco Chen
540af09602 soc/intel/tigerlake: Allow mainboard to override DRAM part number 
In order to support mainboards that do not store DRAM part number in
the traditional way i.e. within the CBFS SPD for soldered memory, this
change provides a runtime callback to allow mainboards to provide DRAM
part number from a custom location e.g. external EEPROM on volteer /
dedede.

For other boards it should be a NOP since the weak implementation of
mainboard_get_dram_part_num does nothing.

BUG=b:152019429

Change-Id: If940a76d36a7645a7441ba418aa7aec9af9f6319
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-04-07 06:31:12 +00:00
Tommie
1b7fc32a54 mb/google/octopus/variants/phaser: Disable xHCI compliance mode 
Since the first LFPS timeout causes xHCI to enter compliance
mode, the SS hub cannot be enumerated. The resolution is to
disable xHCI compliance mode.

BRANCH=octopus
BUG=b:149723583
TEST=Verified USB operation successfully.

Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com>
Change-Id: I3e6ab6ec0c4865cf2467da900f13d18468ff356f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marco Chen <marcochen@google.com>
 2020-04-07 03:50:08 +00:00
Angel Pons
16f6aa81b6 soc/intel/tigerlake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I482715c166ccf5d2f3cc25118d25b07dbfd6650a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:35:15 +00:00
Angel Pons
230e4f9df2 soc/intel/quark: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I3fdfa159194cccf15c0284700f554d2241dad6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:34:14 +00:00
Angel Pons
fabfe9da77 soc/intel/jasperlake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I2efdeb224c478995d393aa3eaac762c876832391
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:33:36 +00:00
Angel Pons
32abdd66a8 soc/intel/icelake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I1edbc8bb0efaad033385f29f8a4747bd178296b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:29:28 +00:00
Angel Pons
80d9238610 soc/intel/denverton_ns: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ib1e226e7816efbc5cffc95563b440fb2ad5b1f95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:28:26 +00:00
Angel Pons
f5627e8454 soc/intel/cannonlake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I48422453735d50eb9292f39a3c031073d647a17c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:27:22 +00:00
Angel Pons
f94ac9ad7d soc/intel/broadwell: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I8995372760543e9cf2c845019f7a063046c55e9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:26:01 +00:00
Angel Pons
c3f58f6aca soc/intel/baytrail: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ib41169395ab239e520f6047ac6bd307ec50776d4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:24:19 +00:00
Angel Pons
0612b27b9d soc/intel/common: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-04-06 19:15:50 +00:00
Angel Pons
ba38f37d18 soc/intel/braswell: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I45d746ed374361036d59167293a90d8e557754fa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:15:37 +00:00
Angel Pons
3bd1e3db9c soc/intel/skylake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I7354edb15ca9cbe181739bc2a148f16bb85ab118
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
 2020-04-06 19:12:54 +00:00
Angel Pons
8559277fc9 soc/intel/xeon_sp: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I703a656c397345025dab398fb642f3de7bbb61fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40220
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 19:12:37 +00:00
Angel Pons
6bc1374e2d soc/intel/apollolake: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I3c6daa484a4aa133ff2ad79eb2b8efa159da3523
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-04-06 19:12:26 +00:00
Angel Pons
47f26dbe15 mb/google/rambi: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I0dea26da28a2879e34593907fef6f984317c347f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40191
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:56:02 +00:00
Angel Pons
2712398a69 mb/google/poppy: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Idfc7a5713e231c4756b5faca8984c6598fe1e65a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:55:51 +00:00
Angel Pons
d28443e5c6 mb/google/slippy: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I74fd273aff05e6635d4964f3614c2f1dd5562b4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:55:32 +00:00
Angel Pons
08b5280c9f mb/google/octopus: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I8076155330100982de82d410b6579ac99ed89e7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40187
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:55:20 +00:00
Angel Pons
2e8a4b0498 mb/google/stout: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ic3314eb6137a6fc9fa1f90685f37223ca1580cb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40197
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:55:08 +00:00
Angel Pons
d9d1d20c97 mb/google/sarien: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ia64c49aed694eac1f98d176c646a60597c8ae66a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40193
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:54:54 +00:00
Angel Pons
11ba353806 mb/google/kukui: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I377ee2c9dfa3113f88237bd6ea79031a79f18ad5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:54:39 +00:00
Angel Pons
b5a2a52bee mb/google/kahlee: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I78f386eb47fc9b91992884e309dbbf33fb3d4e92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40179
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:54:27 +00:00
Angel Pons
952f6b0a77 mb/google/reef: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I57e6790e49032902703ba84b68f285749aab2573
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-04-06 13:54:16 +00:00
Angel Pons
feedf23de0 mb/google/link: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Iddcf70e9a0976cfe2e5fb6d557bfcd22ab1f68cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40181
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:54:04 +00:00
Angel Pons
96d93d142e mb/google/parrot: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I0f41016ea678f63f386c1ae7006b7221a05f6fd9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-04-06 13:53:47 +00:00
Angel Pons
e816d807b9 mb/google/volteer: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I8e2aaf681ba3543cfcd400d21f8e94454e9b1c98
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40202
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:53:37 +00:00
Angel Pons
2e53038cf9 mb/google/veyron_rialto: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ib28acdb91c5eb0c06413edfab62d6737932946f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40201
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:53:17 +00:00
Angel Pons
7caffce31f mb/google/storm: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: I22232d098d34b9a642da157d07978b8d044926ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-04-06 13:53:07 +00:00
Angel Pons
68dd0d53d6 mb/google/nyan_blaze: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Ie2f0dac5a0dee26b965616d410e343569588db7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2020-04-06 13:52:53 +00:00
Angel Pons
94d079ac5d mb/google/veyron_mickey: Use SPDX for GPL-2.0-only files 
Done with sed and God Lines. Only done for C-like code for now.

Change-Id: Icabeae8d5c6c8be8dc284354e1523cec04c9fe30
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-04-06 13:52:39 +00:00