Nautilus-Wifi with m3 AP got a halt issue during CTS test.
Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.
Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.
Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.
BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.
Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP 2.1 implementation is adding features on top of fsp2_0.
One such feature is a shared stack implementation that requires
coreboot to allocate stack for fspm and then fsp uses the same
stack as coreboot. This implementation adds support for shared
stack feature.
Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/28358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We already explicitly generated a dependencies file for the romcc
bootblock. Though, as it has its own rule and isn't registered
to any of our object-file classes, the dependencies file wasn't
included automatically.
Change-Id: I441cf229312dff82f377dcb594939fb85c441eed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/28442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.
Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Check payloads, the root Makefiles and toolchain.inc
- 3rdparty is already not checked, so remove
- The marks around COPYING, LICENSE, and README were not needed
- Skip checking .ico files
Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"
I found that changing this to other forms takes MUCH longer, so I left
the original method mostly unchanged except for moving the include &
exclude lists into variables.
Currently, I'm setting all non-linux operating systems to use the second
version. I'll update that if I find other that other OSes support the
first.
Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.
BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'
Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins
execution will enable cache, then CAR will disappear. So the
Stack will be separated.
Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable dGPU power handling on Lenovo ThinkPad T430, T530 via PMH7
register 0x50.
Although there's no Thinker-1 chip on these models according to
schematics, dGPU power control via PMH7 works the same as on T420/T520,
so they can be considered Thinker-1-compatible.
It can be tested from linux userspace using util/pmh7tool.
To turn dGPU power off:
pmh7tool -c 0x50 7
pmh7tool -c 0x50 3
To turn it on:
pmh7tool -s 0x50 3
pmh7tool -s 0x50 7
To check whether it is on (bash):
reg=0x$(pmh7tool -r 0x50)
echo "$(( (( reg & 0x08 )) >> 3 ))"
or just `pmh7tool -b 0x50 3` with
https://review.coreboot.org/#/c/coreboot/+/28388/
Tested on ThinkPad W530.
Change-Id: Ieab1a33b3c680c757cc0999660b5cb7e122474cc
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28392
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node.
Without DRIVERS_SPI_ACPI, the kernel will popped out the below error:
cr50-update[592]: Starting cr50 update
cr50_get_name[595]: updater is /usr/sbin/gsctool -s
cr50-update[609]: exit status: 3
cr50-update[613]: output: Could not open TPM: No such file or directory
cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod'
cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod
cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state
cr50-update[682]: not running
cr50-result[782]: Not running normal image. Skip setting Board ID
trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory
BUG=none
BRANCH=master
TEST=/dev/tpm0 is created
Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Like the 3rdparty/blobs repo this isn't checked out by default. Right
now you can manually check it out using
$ git submodule init --checkout
A follow up commit will add some automagic if USE_BLOBS and
MAINBOARD_USES_FSP2_0 are enabled.
Change-Id: Ie612495abc2a2d5947225e6ab54872aa72d4bec6
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/28303
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch overhauls the Cheza FMAP, removing some sections we don't
seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of
RW_DDR_TRAINING), and adding new sections we're going to need soon or
should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY).
Make more use of implicit offsets and sizes, because we can and because
it should make future adjustments easier.
Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: T Michael Turney <mturney@codeaurora.org>
On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.
BUG=N/A
TEST=N/A
Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
These RISC-V ABIs defined by GCC : ilp32 ilp32d ilp32f lp64 lp64d lp64f.
Through this we know that the length of the long's bit is equal to pointer.
So update this code. This's more flexible.
Change-Id: I16e1a2c12c6034df75dc360b65acb1b6affec49b
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27768
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefore code needs to be
updated.
BUG=b:69231009
TEST=Build and boot grunt.
Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Also removed internal pull ups for CX_PREQ_L and
CX_PREQ_L signals as they have external pull ups.
BUG=b:110654510
TEST=On Yorp Proto 2, flashed image and verified that it boots to OS.
Checked Wake-on-Wifi works with both cnvi and pcie modules.
Also executed a few suspend resume cycles.
Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/28328
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC base address is different for CNP LP pch and CNP H pch.
Added logic to determine PMC base addrress dynamically based on PCH ID.
BUG=none
BRANCH=none
TEST=Boot Coffeelake U RVP board and check if PMC base address is
determined correctly.
Change-Id: I833395260e8fb631823bd03192a092df323250fa
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27523
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should always update BCLP, no matter if the driver is ready yet to
process the request. This way it will hold the current value when the
driver initializes.
Change-Id: I4b091d744f95da39abe542966f0a8589a187573b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.
Only affects brightness control using mailbox3.
Fixes: 6838aaebf9 ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Grunt takes a few seconds to update the EC, so display a notification
screen while that's happening.
BUG=b:113286040
TEST=Boot Grunt with old EC firmware, see update screen
Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In function _gpio_base3_value(), if num_gpio is 0 it'll cause the return
of an undefined value, as no for loop will be executed. Assert that it's
not 0.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I2b6537900fa41ebbee0171959f3ce236d360bc80
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some ACPI interfaces introduced by Chrome or coreboot do not
need drivers outside ChromeOS, for example Chrome EC or
coreboot table; or will be probed by direct ACPI calls (instead
of trying to find drivers by device IDs).
These interfaces should be set to hidden so non-ChromeOS systems,
for example Windows, won't have problem finding driver.
Interfaces changed:
- coreboot (BOOT0000), only used by Chrome OS / Linux kernel.
- Chrome OS EC
- Chrome OS EC PD
- Chrome OS TBMC
- Chrome OS RAMoops
BUG=b:72200466
BRANCH=eve
TEST=Boot into non-ChromeOS systems (for example Windows)
and checked ACPI devices on UI.
Change-Id: I9786cf9ee07b2c3f11509850604f2bfb3f3e710a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1078211
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Trybot-Ready: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
